VLSI Architecture Design And Real-time Implementation For SIFT

Image registration is the process of overlaying two or more images of the same scene taken at different times, from different viewpoints, and/or by different sensors. SIFT (Scale invariant feature transformation) features are invariant to image scaling and rotation, and partially invariant to change in illumination and3D camera viewpoint. So image registration based on SIFT features is widly used in many image analysis tasks. With the rapid development of video processing, image sensor will be developed toward high resolution and frame rate. Combination of high resolution and frame rate leads to higher requirement of real-time processing. However, because of high computation complexity, it is hard to extract SIFT features in real-time.Aiming at extracting SIFT features in real-time, this thesis proposes a VLSI pipeline architecture, which can extract SIFT features of1024×1024image at30frames per second. The research work mainly contains:Firstly, optimized SIFT algorithm which meets the requirement of false positive rate and suits for hardware implementation is proposed. The optimized algorithm is a minimum hardware cost implementation, considering referecing one frame for reducing memory capacity and completing iteration once for improving throughput rate of pipeline architecture. Then SIFT is separated into two tasks of feature detection and feature generation part. On the one hand, data level parallelism is exploitd by high throughput pipeline architecture; on the other hand, the whole pipeline architecture is introduced through parallelization of the two tasks. Finally, throughput of each individual pipeline architecture is proposed aiming at processing1024×1024image in real-time.Next, pipelined architecture for feature detection is proposed, which contains DoG scale space construction and feature point location module. On the one hand, parallel smoothing scheme is adopted to reduce the number of delay lines by about80%; on the other hand, time division multiplexing is used to improve efficiency of gaussian filters to98%, which leads to hardware cost reduction of arithmetic unit.Thirdly, mechanism and hardware implementation of central memory is propsed based on interest region. Interest region is filled and released in lines, similar to the way of FIFO; memory array is implemented by signal port memory organized by four-pixel combination and multi-banks. Cycle-accurate simulations shows that interest region of72lines and FIFO depth of64can meet the system requirements. The circuit architecture is designed in two level logics:the bottom level manages muti-banks and the top level manages read and write pointers of FIFO. With clear architecture and simple logic, the circuit can meet the frequency requirement of100MHz.Finally, Pipelined architecture for feature generation is proposed whose throughput is2pixels per cycle. Firstly, histogram unit which has configurable dimension and update channels is designed. Hardware cost model of dierrent dimension and channels is made by synthesis. According to the principle of trilinear interpolation, histogram unit of size128is converted to sixteen histogram units of size8inorder to reduce the hardware cost. The synthesis result shows that the number of equivalent gates is reduced by about40%.The overall result shows that the system can reach maximum frequency of100MHz, in SMIC0.18μm CMOS process technology, which includes1154K equivalent gates and2.2858Mb on-chip RAM. Further experiment result shows that the proposed architecture can process1024×1024image at30frames per second. The proposed architecture performs better than other published architectures, in terms of frame rate, memory reqirement and equivalent gates.