Lte Fft And Channel Estimation In Downlink Receiving System Research And The Realization Of Multicore

With the development of information technologies and the huge demand of different kinds of application, mobile communication technology is in evolution towards higher and higher data rates.3GPP Long Term Evolution (LTE) has been the most important standard among the4G communication standards because of its high speed data rates, high spectral efficiency, flexibility, low latency and wide-used applications. Where there are more and more bottlenecks in the development of traditional serial computing and serial computer architecture technology, parallel computing and multi-core architecture technology has become the next hot spot in the research of information processing system.In this paper, the key technologies in LTE downlink transmission system were focused on, especially FFT technology and channel estimation technology, and the implementation of these technologies with multi-core architecture was discussed. The main contribution of this dissertation can be concluded as following:1. Begin with the algorithm, the FFT algorithms and channel estimation algorithms were introduced, and various algorithms in FFT technology and channel estimation technology were compared in complexity and feasibility. Then the pros and cons of different hardware implementation of FFT and channel estimation were discussed.2. According to the requirements from LTE standard to the FFT module, a proper FFT algorithm was used and paralleled. The algorithm was implemented on a multi-core platform which has2clusters and each cluster has8cores. The algorithm can be used to calculate128,256,512,1024,1536and2048-point FFT in LTE downlink transmission system. The2" FFT was transformed to n radix-2FFT in a decimation-in-frequency (DIF) way. The calculation time was reduced and the power efficiency was raised by using the pipeline parallelism and data parallelism structure.3. According to the requirements from LTE standard to the channel estimation module, different feasible channel estimation algorithms were compared and the algorithm with the best performance was used. The algorithm was also designed in pipeline parallelism structure and data parallelism structure. The algorithm can be divided into3steps. First step, LS algorithm was used to get the channel estimation on pilot position. Then the second-order Gaussian interpolation was used in frequency domain. Last step, the linear interpolation was used in time domain.4. The FFT algorithm and channel estimation algorithm was realized on a multi-core processor which is implemented by TSMC65nm process. Functional verifications were done in stimulation platform. Test results were compared with ASIC implementation, DSP implementation and other processor implementation in speed, power, energy efficiency, etc.