Dsign Of High Voltage Power Mosfet Termination

Power VDMOS is always playing an important role in Power Semiconductor Devices because of its high input resistance, low drive power, high switch speed, good frequency character, high thermal stability and many other advantages. In recent years, as the demand become more and more urgent in new energy, automotive electronics, power supply, lighting and so on, power VDMOS shows more and more importance in social and economic development.As the power VDMOS become used in wider rang of application, higher performance is required in Breakdown Voltage, the basic Parameter of Power Devices. The low voltage is easier to design, and has a great variety of products. But when the operating voltage become very high, many special effect makes the design becomes much more difficult. Meanwhile, if the conflict between cost and performance is not well controlled, it is hard to get a stronger competitiveness.The Blocking capacity of high voltage VDMOS chip is always decided by the edge termination. A termination is used to share the high electric field of the periphery of the cell region by special structure, so that the chip will not easily breakdown because of the electric field focus outside the Pbody region. The content of this paper is to study the design of edge termination structure based on the practical productive technology.First of all, the historical development and present condition is briefly introduced. Then this article describes the breakdown form of the semiconductor devices, analyses the basic theory of avalanche and the avalanche of PN junction in different condition, and explains how the edge termination promotes the Breakdown Voltage based on practical chip structure. After that, simulation is done based on Sentaurus TCAD to design a 700V Field Plate(FP) Field Limit Ring(FLR) termination, 900V Junction Termination Extension(JTE) termination and a 900 V Variation of Lateral Doping(VLD) termination.In the introduction of the design of the FP-FLR termination, the semiconductor technology process is firstly described, and emphasized the influence of the key process steps on the chip structure. Then the design procedures of a floating FLR termination is discussed, and verified from simulation. After that, a 700V FP-FLR termination with the simulation Breakdown Voltage of 733.4V is designed, and other parameter is optimized to appropriate. Then a Trench FLR termination structure is designed by the combination of normal FLR termination and Trench termination. Without addition masks the junction depth is deeper by etching a trench, and the reducing of surface maximum electric field has some kind of increasing of reliability of the chip.To get a lower area and higher efficiency of the edge termination, a 900V VLD and a 900V JTE termination is designed, the simulation Breakdown Voltage is up to 938.5V and 992V, the efficiency can reach %93.3 and 98.6%, and the termination length is only 137μm and 130.2μm. Compare to the 198um termination length and 84% termination efficiency of the 700V FP-FLR termination, VLD and JTE terminations have a large margin reduce in chip area and promotion in efficiency. On the other hand, normal graded junction is used to analyze and understand the principle of JTE, and verification shows a good coincidence.