The Analysis And Suppression Technology Of The EMI On Power VDMOS

Power electronic devices are transmitters of electromagnetic interferences(EMI).Electromagnetic compatibility becomes an important issue due to the recent technical development and the ever-increasing improvement of switching power semiconductor performance in terms of high frequency.Power VDMOS(Vertical Double-Diffused MOSFET)devices are now used for power switches in various industrial applications.In these cases,power VDMOS operates at the rapid on/off transition state periodically,and the voltage transition rate dv/dt and the current transition rate di/dt change rapidly at the switching transient of the device,which causes high level of electromagnetic interference to the neighboring circuits.Therefore,the EMI on power VDMOS is studied in this thesis.By optimizing the parameters of VDMOS devices to reduce the EMI when VDMOS devices operate in power supply systems could not only greatly simplify the EMI design for circuit engineers,but it also could reduce system cost and enhance reliability,which can promote the market competitiveness of the devices.First,the EMI generation mechanism of power VDMOS has been analyzed theoretically in this thesis.In the high frequency switching process,gate capacitances are discharged and recharged rapidly,thus triggering high di/dt and dv/dt,which is the main cause for EMI generation.Specifically,the EMI generation mechanism of power VDMOS includes four aspects mainly: oscillation caused by the parasitic capacitances,the gate voltage oscillation,the drain voltage oscillation and oscillation caused by the parasitic body diode.Then,the suppression technology of the EMI on power VDMOS is proposed from the perspective of optimizing the parasitic parameters of VDMOS device and the soft factor of the body diode.Furthmore,TCAD simulation tool MEDICI is used to validate the parameters that have impact on the VDMOS EMI.The VDMOS turn-off characteristics are simulated by changing the value of different parasitic parameters,to analyze how the parameters influence the VDMOS turn-off characteristics.The oscillation amplitude of the current and voltage waveform in turn-off transient is used to represent the level of the generated EMI.The simulation results show that the greater gate resistance RG and gate capacitance,the smaller parasitic inductance LD can suppress the current and voltage overshoot across the power VDMOS,which results in smaller oscillation amplitude andoscillation times of the current and voltage waveform in turn-off transient,thus reducing EMI.The results are coincident with the theoretical analysis.Finally,two kinds of VDMOS products are tested,and the tests include complete appliance EMI test when applying power VDMOS in practical application circuit and power VDMOS dynamic characteristics test.The test results further validate that greater di/dt and dv/dt during switching will induce more serious EMI.Therefore,proper increase of the parasitic gate resistance RG,parasitic capacitance CGS and CGD,proper decrease of the parasitic inductance LD and improvement of the soft factor of the body diode are effective measures for EMI reduction on power VDMOS.