Design And Research Of PWM Core Applying In The Frequency Control Field And Supporting Mechanism Of Hardware’s Interconnection And Trigger

With the rapid improvement of design technique, SoC technology has become the main stream IC design technology gradually, and IP technology led to the further development of SoC. SoC integrates a number of IP cores that are used in the different working fields. In order to meet the requirements of pulse width modulation(PWM) with the power elcetronics and apply it to more other fields, this paper designed a PWM IP core based on the mechanism of hardware’s interconnection and trigger in the frequency conversion controlling field. Comparing with the conventional PWM, it had more efficient applicability, more different configuration and higher instantaneity and so on.The paper firstly introduced the SoC’s whole architecture of frequency conversional control. Based on SoC technology, it described structure and characteristics of processor named CK803S and APB bus of AMBA specification. In addition, it introduced other assistant IP cores’characteristics and working action such as ETB and SPI. Then it intensively stated global structure of PWM core and RTL level’s design process and implementing principle of every submodule, and gave a specific example about PWM. It also proposed PWM’s Innovations, including mechanism of hardware’s interconnection and trigger and resource reuse. After that, according to the verification methodology, simulated verification and FPGA verification were implemented for PWM. We used the VCS tool of Synopsys for simulated verification. And we used GDB debugging tool and testing tools for FPGA verification in the FPGA named Vertex-5, such as logic analyzer and oscilloscope. It can obtain verified result that meeting the functional and timing requirements through analysis. Finally, it didn’t only emphasized whole process of logic synthesis, but also explained technology library files and constraint files. According to result of synthesis, we detailedly analysed timing and assessed area usage and power consumption of each mode for PWM. Eventually it achieved timing closure. All the situations of area and power can achieve an acceptable level. We simply introduced relevant technology of DFT in the end.This paper mainly described a design process of front. Basing on solving the defect of common PWM core, we designed PWM core that had enhanced function, individuation and applications in a variety of occasions.Althrough this design had some potential defect, the PWM didn’t only achieve basic PWM output signal, but also according to program written by user distributed registers and chose other working modes, such as input capture mode and output compare mode on the whole. It reflected high applicability and flexibility. Then it can trigger and connect other IP cores so that it can support fast instantaneity. The purpose of this design was to provide a multifunctional,configurable and high-performance’s PWM core.