Extension Of Byte Addressable Mode And Simulation Of 64-bit Data Type Support In BWDSP104X

BWDSP104X is a high-performance,32-bit and floating-point Digital Signal Processor, whose architecture provides both basic arithmetic and logic instructions, handling floating-point as well as fixed-point operations, and data transmission instructions, double-word instructions, and non-operation instructions. With GCC as its front end and a module of strong optimization function as its back end, Open64 compiler has been transplanted to BWDSP104X for C language development.BWDSP104X, a 32-bit word addressable processor, supports only 32-bit data type, which brings difficulties in the process of data types of other bit widths. For example, in the process of 64-bit data, precision loss will appear and word addressable mode will be incompatible to the average byte addressable mode. With the increasing requirement of high precision operations,32-bit data operation should be extended to meet current requirements. The main tasks of the thesis will be explained as follows.1) Simulation & Extension of Byte Addressable Mode in B WDSP104XThe modification of non 32-bit data type on the front end of the Open64 compiler produces intermediate codes which are based on byte address mode. For the lack of corresponding hardware instructions’support, a set of instructions will applied to simulate the original instructions at the stage of back-end code generation, probably leading to code bloat. To achieve optimization, this article can be some detection method to limit the use of the byte pattern, that will somehow restrain code bloat.2) Simulation of 64-bit Data Type Support in BWDSP104XThe extension of 32-bit data type to 64-bit data type will spread application rage of the processor. For the lack of hardware instruction support, modification of both front end and back end of Open 64 have been implemented. The data types at the front end has been modified to produce corresponding intermediate codes. At the back end,32-bit registers have been applied to simulate the read-write operation of 64-bit data. The codes of assembly library functions call have been produced to guarantee such 64-bit floating data operations as add, subtract, multiply, divide, power, and exponent. Finally, cover test of library, as well as functionality verification of 64-bit floating data type, have been implemented to guarantee the function validity of 64-bit data types which have been simulated in the compiler.The Compiler Trainer test set have been implemented to guarantee the function validity of data types in the compiler. Namely, the extension of byte addressing mode as well as the simulation support 64-bit data type have been accomplished in the compiler.