The Research Of Timing Synchronization And Channel Estimation Algorithms In IEEE 802.11ac

With the development of Internet and Internet of things,WiFi communication is becoming more and more important.Integrating all digital algorithms?radio frequency circuit and microcontroller unit into a WiFi chip to speed up the interconnection of all things has become the one of most important research of WiFi technology.A complex chip from design to chip verification is a relatively long process,which need many participants.Designers are usually divided into two parts: front end design and back end design.This paper mainly describes the visual angle of the front end design.It describes the design of physical layer package,receiving algorithm design and optimization,hardware design and FPGA verification.This paper mainly aims at the physical layer of the IEEE802.11 ac protocol in the WiFi protocol,and builds the physical layer simulation environment of the whole transmitter signal modulation and receiver signal demodulation from the launching package process to the receiver.Because the receiver timing synchronization and channel estimation algorithm are the focus of the algorithm,they are designed and optimized.The corresponding hardware modules are designed for the improved timing synchronization algorithm and channel estimation algorithm.Finally,they are verified by the FPGA.The main research results of this paper are as follows: 1.An up-sampling packet algorithm for the transmitter is designed.It is mainly based on the MCS to design the packing algorithm.A complete data packet include two parts of the packet header and the OFDM symbol.Finally,the data packet is up-sampled by 4 times.2.Designed and improved the overall timing synchronization algorithm.The timing synchronization algorithm is mainly divided into three parts,packet detection algorithm,symbol synchronization algorithm and all-digital loop synchronization tracking algorithm.In this paper,a cross correlation algorithm is selected for packet detection,and its reliability is improved.A cross correlation energy normalization algorithm is proposed and a threshold determination algorithm is improved.The improved symbol synchronization algorithm also adopts the cross correlation energy normalization algorithm,which can reduce the length of the window by jumping point algorithm.It is greatly reduce the amount of calculation.The full digital loop synchronization tracking algorithm mainly optimized the selection of the error detection algorithm and the coefficient of the loop filter algorithm,and an improved loop coefficient.Then,a method of how to quickly obtain the optimal loop coefficient is proposed.3.Overall channel response estimation algorithm was designed and improved.The research of channel response estimation algorithm is mainly divided into two parts: channel modeling and channel estimation.The part of the channel modeling introduces the types of channels,and lists the simple tap models and exponential models.On the basis of the existing algorithms,the channel estimation algorithm applies the unique VHT-LTF sequence of IEEE802.11 ac.It uses the joint estimation method of L-LTF and VHT-LTF sequence,and presents a new algorithm for channel estimation and compensation.4.Hardware design of timing synchronization and channel estimation was proposed.The frame detection algorithm and symbol synchronization algorithm are the same as the basic algorithm,which can be designed in a module,saving the hardware resources and improving the speed of operation.The design of channel estimation algorithm joins parallel FFT module.Finally,FPGA development board,spectrum analyzer and vector signal generator are used to verify the hardware structure,which proves the practical value of the timing synchronization and channel estimation algorithm for the IEEE802.11 ac physical layer.