Research Nd Implementation On Data Acquisition System Based On Hybrid Filter Banks

Nowadays, with the digitization degrees in modern digital signal processing becoming higher and higher, the requirement for analog to digital converter(ADC) is also higher and higher. High speed and high precision sampling systems have been widely used in digital systems. Based on actual demand, this thesis studies multi-channel sampling systems and realizes the system on a FPGA platform. Through theoretical analysis, simulation and experimental test, the system performance and algorithm feasibility are analyzed, and a high quality sampling system is obtained by optimizing structures and using simple and feasible structures. The main contents include:1. Consulting the domestic and foreign literature, the basic design method and theory of multi-channel sampling is studied.2. Power complementary structure is main research direction. The design method of filter banks is derived, and performances of difficult systems are simulated and compared. The error analysis method of time-alternated sample is used to analyze channel error, simulation error and quantization error, and an analog coefficient model is used to characterize the system error, which simplifies the representation and measurement of the errors.3. The thesis focuses on system optimization. According to the error model, an algorithm based on energy spectrum of test signal is used, and a pattern search method is proposed to optimize filters’ coefficients. Combined with the characteristics of polyphase interpolation filter and power complementary filters, a simplified filter banks structure is designed, which is easy to implement and correct in FPGA. The structure of single analog filter is studied and improved structure is put forward.4. FPGA is selected as the hardware platform, and AD9434 and XC7K325 T are used to complete a two-channel sampling system. The required sampling rate is 1Gsps, and sampling precision is 9.0bit. Two terminal network is used to design analog filters, which performance are simulated and measured. Verilog language programming is used to realize control and calculation work on FPGA, and finally the error correction and adjustment are finished. Test signals are generated by signal generator. Through online tracking and synthesis analyzing signals, single frequency and narrow band signal sampling rate is 1Gsps, sampling effective number is between 8.5bit and 9.2bit, which basically meets the design requirements.