Power Complementary Hybrid Filter Design

In today's electronic war, digital signal processing has been widely used. As the signal in the war field covers the wider instantaneous bandwidth, real-time signal processing shows the higher requirements of converting analog signal to digital signal. Meanwhile, with the promoting of the rapid development of FPGA and other hardware platforms, the speed of digital signal processing gains an unprecedented upgrade. It is also an urgent requirement to improve the speed and resolution of ADC system.Power complementary hybrid filter bank is an efficient method for realizing high speed and high resolution data acquisition system and it is mainly used in wide band and high resolution digitizer and other testing equipments. The wide band and high resolution digitizer demands to achieve 400MSa/s sampling rate and 12-bit resolution. However, due to the constraints of existing chip technique, it is difficult to achieve the target using one piece of ADC directly. Therefore, technology of power complementary hybrid filter bank containing two pieces of ADC is used for this purpose to enable the high speed and high resolution ADC system.This dissertation researches the design method and the associated theory of power complementary hybrid filter bank aiming at the above target. The main contents are as follows:1. Technology of power complementary hybrid filter bank and the theory of completely reconstructing signal in analog/digital conversion system are investigated in detail.2. Genetic Algorithm and application of the Genetic Algorithm Optimization Toolbox is demonstrated, which is developed to optimize the transfer function for third-order analog analysis filters. On this basis, RLC circuits and component values of the analog analysis filters are got according to doubly terminated ladder networks.3. Optimization of the synthesis filters is presented and the frequency responses of the ideal synthesis filters are determined based on the theory of completely reconstructing signal. Genetic Algorithm Optimization Toolbox is introduced again to optimize the system delay. At the same time, according to the Inverse Fast Fourier Transform, the synthesis filters coefficients are obtained. Finally, parallel distributed arithmetic is employed to implement the FIR digital filters in the FPGA.During the design, through a series of optimization and tries, the design methods and steps for the power complementary hybrid filter bank are ascertained. The system adopts three-order analog analysis filters and 29-order synthesis filters, introduces 1. 4×10?6dB peak distortion and -125dB average aliasing error, which can meet the requirements of 400MSa/s sampling rate and 12-bit resolution.