Reliability Research On High Voltage Gate Driver Integrated Circuit

High voltage gate drive integrated circuit (HVIC) is a high and low voltage compatible IC, which is an alternative to the traditional method with discrete transistors to drive the power devices, thus the power dissipation and the system size are improved. At present, HVIC is the key component of the control system for energy saving motor and they are widely used in inverter home appliances, electric vehicles, small-medium industrial equipments and so on, which put forward higher request to the reliability of the HVICs.High voltage isolation is the most important technology of the HVIC. As we known, there are no high voltage interconnection and high side leakage issues in the Divided-RESURF isolation structure. However, the immature breakdown and the electrical performance degradation under high temperature reverse biased (HTRB) condition are the design risks due to that the LDMOS devices are embedded in the isolation structure. In addition, in the inductive loaded system, the HVIC can be easily trigged on or latch up under negative VS surge stress and fast dvs/dt stress. Those reliability issues have blocked the further application of the HVICs to the motor control system. In this thesis, base on 1μm 600V bulk-silicon technology, the reliability of the HVIC is analyzed and investigated systematically.1, a novel double N-well Divided-RESURF isolation embedding the LDMOS structures is proposed. The N-well can reduce the influence of the P-well on the charge balance of the LDMOS, thus the peak electrical field at the high side corner is reduced. With the same drift length, the BV of the proposed isolation structure is improved by 15.8% and its high side leakage is lower than 1μA.2, the degradation mechanism of the embedded LDMOS structure in the isolation structure under HTRB is investigated and a new structure with lower surface electrical field is proposed. The effect of the mobile positive ions on performance of the LDMOS is suppressed. The new isolation with the embedded LDMOS can pass 1000h HTRB evaluation successfully.3, the generation of the negative vs surge is analyzed and the failure mechanism of the HVIC is investigated. A new circuit for improving the negative vs surge immunity is proposed. By sampling the surge noise and then control the source current of the HVIC, the holding time of the noise is reduced and the noise immunity is improved. The measurement shows that the HVIC works normally when the negative surge is higher than -98V.4, the generation of the dvs/dt noise and its effect on HVIC is investigated in detail. After the analysis of the conventional noise canceller circuit, a new double pulses trigged capacitive loaded level shift circuit is proposed. The spurious trigger due to the displacement current is avoided effectively. The measured results show that the dvs/dt immunity is improved to 85V/ns.5, the input logic, pulse generator, under voltage lock out (UVLO) circuit, electronic static discharge protected circuit and other key circuits of the HVIC are analyzed and designed in this thesis. After the investigation on the layout design, the HVIC is taped out.6, the static/dynamic parameters, negative vs surge and dvs/dt noise immunity are measured. Moreover, the proposed HVIC is successfully evaluated in the motor drive system of the model aircraft.