Design And Implementation Of The Wireless Image Data Collection And Transfer System Based On FPGA

With the development of network information, image acquisition and transmission technology has become one of the most rapidly developing technology in recent years. Nowadays digital image acquisition and transmission technology are widely used in telecommunications, aerospace, industrial and medical fields. Digital image capture and transmission problem is the amount of data is so large, slow processing speed and low efficiency of implementation, and image algorithms software has low flexibility and its processing is very time-consuming. However, based on field programmable gate arrays FPGA for image acquisition and transmission hardware system can be done real time high speed image processing algorithms to handle large amount of data and processing speed. With the rapid development of microelectronics technology, FPGA for the digital image processing brought new methods and ideas on algorithms and hardware architecture.Based on FPGA with hardware description language, interfaces with the hardware of the functional modules, control the external hardware devices as image capture and transmission system. The main research work is as follows:(1) Building FPGA-based hardware systems, the system uses Altera’s Cyclone III series FPGA chip as the central processor, and with peripheral circuits and a plurality of peripheral devices. Using Verilog HDL hardware description language for each interface and function modules of the system hardware.(2) In-depth analysis of peripheral devices such as CMOS camera, SDRAM, Ethernet interface working principle. And using hardware description languages Verilog HDL to write modules to implement the I2C bus for the COMS camera initialization, write video receiving module is used to receive the video signal from COMS, write SDRAM controller module is used to control SDRAM access to images, and write Ethernet controller module to implement the instructions to receive and send 640*480pixel image data.(3) The USART received command processing, when receiving the instruction to send pictures, caches the source image information in the SDRAM read asynchronous FIFO buffer, and then connect an external WIFI module via USART interface code stream is sent to the remote PC machine. And the code stream on the PC can be restored to the original captured image.The individual modules of the entire design and simulation and logic synthesis in Altera’s Quartus Ⅱ development environment as well as third-party simulation software Modelsim.