Design And Verification Of 10Gigabit Ethernet MAC Controller

With the development of computer and network technology, especially the rapid rise of the bandwidth applications, network data exchange technology is becoming more frequent and complicated. The requirement about Ethernet bandwidth increased fastly, and the conventional speed of 100/1000Mbps has begun to drag on the users’experience. So the application of 1OG Ethernet technology in the backbone network and subscriber access network will become increasingly widespread. And the design of the MAC (Media Access Control) controller of 1OG Ethernet has great significance.The 10G Ethernet MAC controller which mainly complete the function of encapsulation, decapsulation and management of Ethernet frame in this design, is an important part of the project " The Intellectual Property Design based on the Copper Interconnected of Ten Gigabit Ethernet Physical layer". First of all, the article maked an analysis on the related functions, frame format, flow control principle,10 Gigabit Media Independent Interface(XGMII) and other aspects about the MAC controller through the interpretation about the series of IEEE802.3ae protocol standards, and completed the overall design of the framework. Then followed the top-down design approach, the 10G Ethernet MAC controller was divided into the sending module, receiving module, flow control module and XGMII interface module according to the system framework. The detailed designs in the internal structure, external interface signal and interconnect communication mode between the submodules are gived in this paper. This article proposed a parallel CRC32 checksum algorithm to verify the data packet. Meanwhile, it optimized the structure of 10G Ethernet MAC controller by summarizing the keeping DIC (Deficit Idle Count, DIC) algorithm. VerilogHDL language was used to describe the top module and sub-modules to complete the front-end design. Finally, the article built a verification platform, and completed the verification by ISim simulation tool. And based on the SMIC 40nm standard cell library, the paper used Design Complier (DC) to complete logic synthesis and determined whether the timing, area and power consumption meet the design requirements or not. Based on Xilinx VC709 connection kit, a FPGA verification platform has been build. After the RTL design completed the synthesis and Place & Route in ISE, downloaded bits file into the FPGA, and used ChipScope observe and test waveforms. The verification work showed that the design of 10G Ethernet MAC controller in this article was practicable.Innovations in this paper:Firstly, a simple and efficient strategy was proposed to send and receive PAUSE frames to realize the flow control according to the parallel data processing characteristic of the 10G Ethernet MAC controller. Secondly, an improvement was applied in the traditional multi-channel parallel CRC32 checksum, which use the 64bit and 8bit multi-checksum structure for simplifying the structure of calibration circuit. Thirdly, the paper proposed a keeping DIC algorithm and utilized the algorithm in hardware with a look-up table, which could maintain a minimum frame spacing requirements and to ensure the data transmission efficiency.