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A Study On Integrated Drive Motion Control System

Posted on:2017-01-10Degree:MasterType:Thesis
Country:ChinaCandidate:Y J ZhuFull Text:PDF
GTID:2308330482980610Subject:Mechanical engineering
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With the development of automatic control, computer science and intelligent robotics technology. Motion control system has developed to a high-speed, high-precision, low cost, high stability direction. Driving motion control system is an integrated structure which is integrated into the motion control system on an FPGA chip. As a co-processor, MCU is responsible for task scheduling and state handing. The motion control system will become the mainstream in the future of motion control system with real-time processing capability and good motion control performance advantages.In this thesis, some critical key technology and its development trend are carefully studied. Driving motion control system which is based on FPGA+MCU is proposed. The main contents are as follows.Firstly, In order to build FPGA peripheral circuit and divide motion control module, Hardware module is planned. The pulse transmission module, the quadrature encoder decoding module, interpolation algorithm module, acceleration and deceleration algorithm module are members of motion control system which is based on FPGA. As a co-processor, MCU is mainly responsible for task scheduling, LCD modules, touch screen module and serial port module.Secondly, Using DDS direct digtal synthesis algorithm to achieve frequency pulse transmission module, You can adjust the frequency control word k to achieve 1HZ-25 MHZ any frequency modulation, Through internal divider joined in logic judgment, This algorithm can effectively avoid the clock cycle frequency distortion in addition to countless problems.Thirdly, When it comes to count the quadrature encoding signal, Not only to convert the finite state machine logic state of a plus or minus sign of the count, But also the introduction of time equivalents. That is the logic state hold time is equal to a quarter of quadrature pulse cycle, If the logic state holding time is less than this amount, It would be explained that this shift state is due to the interference signal which is caused by external disturbances,such signals must be shielded to avoid error count.Fourthly, In order to design acceleration and deceleration algorithm, The principle of trapezoidal and S-shaped algorithm are analyzed. Finally digital integration method is selected to achieve linear and circular interpolation. Linear and circular moving are verificated in Disu machine hardware platform.
Keywords/Search Tags:FPGA, Finite state machine, Direct Digtal Synthesis, Digital integration algorithm
PDF Full Text Request
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