Optimal Design Of Electronic Static Discharge Protection For RFIC

With the shrinking characteristic size of the Integrated Circuit and the improved performance/function of chips, much attention has been shifted on reliability design of electric circuits. Among that, the design of ESD is a very important part of the reliability of integrated circuit. But as for RFIC circuit, its ESD should be equivalent to digital/analog integrated circuit. Because of the high-frequency characteristic of the circuits, it is very significant to notice the influence of the parasitic effect and to consider the key factors of the core performance degradation of the internal circuit which resulted from improving protection capability.This thesis mainly focus on the protective design of whole chip RF-ESD in a process. Based on the theory on parasitic effect optimization and parasitic parameter model, as well as some methods of optimization in protective structures of device level and circuit level, and from the aspect of protective design of whole chip RF-ESD, this thesis discusses different issues respectively, which are some significant views in the design of RF-ESD, tests and results on ESD parasitic effect in the design of RF circuit, and the design of protective structure for input or output as well as power clamps.For the I/O protection, this thesis optimizes the design of I/O protection circuits in three aspects, improvement of the device structure device shape and dicoupling, analyzes the parameters of multiple designed networks, including the deep N-well structure which can prevent Darlington Effect and cascade sub-typed diodes, the DTI deep-trench insolation structure which can minimize the parasitic effects inside and outside diodes, polygonal hollow diode structure which degrade parasitic effects without influencing the protective ability, inductive decoupleing structure and the distributed circuit structure,and assesses the advantages and disadvantages of these networks. In addition, this thesis also shows the measurement results of the double diodes protection network with DTI deep-trench insolation structure in improving. The measurement results reveal that the new protective diodes can reduce the parasitic capacitance with approximately 4.6f F as applying, only 85% of that in initial ones.For the power clampping circuits, this thesis introduces the categories of ESD power clampping circuits, including voltage-trigerred cascaded diodes structure, SCR structure, GGNMOS structure, voltage-frequency-trigerred diode resistive ditection power clampping circuits, and frequency-trigerred RC ditection circuits. This thesis mainly analyzes the advantages and disadvantages of categories of power clampping circuits, the essential parameters in circuit design and the respective optimization. Additionally, this thesis proposes a dynamic RC ditection circuits with a three-stage-invertor isolating structure on emphases, and analyzes its protective ability and the results after optimizing the trigerring time. The results indicate the false trigerring time of the new structure is narrowed by 30%, under the same protective ability.In the last part, this thesis gives the analysis and expection of the future work, based on the shortages, and shows directions on research methods and areas to the scholars on this field.