Design And Study On All-digital Controlled LC Oscillator Applied In All-digital Phase-locked Loop

Traditional analog RF integrated circuit design is facing more challenges and difficulties in deep sub-micron CMOS process and ultra-deep sub-micron process. Digital RF was a novel solution which was proposed to solve the problems above. All-digital controlled LC oscillator(DCO), all-digital phase-locked loop(ADPLL) and single-chip digital RF transceiver based on all-digital phase-locked loop first proposed by Texas Instruments were important methods to digitize analog RF circuits. In this thesis, an all-digital phase-locked loop based on all-digital controlled LC oscillator was studied and the work are summarized as follows.(1)The existing minimum variable capacitance structures used in all-digital controlled LC oscillator were analyzed and complementary varactor pairs across capacitor structure was proposed to use varactor with larger size to achieve smaller minimum capacitance value, which can reduce the influence of the fabrication error, solve the nonlinear problems under large signal swing oscillation, and reduce the restriction of the minimum capacitance value by mismatch capacitor capacitance. In the same process, the minimum capacitance value was reduced nearly 50%.(2)An all-digital controlled LC oscillator was designed by using the new minimum variable capacitor structure. Accordingly the capacitor array was designed based on the features of the new minimum variable capacitor structure. For Band level capacitor array, MIM varactor was replaced by inversion-mode PMOS varactor to reduce the complexity of the band level capacitor array. For MC level capacitor array, inversion-mode PMOS varactor was replaced by complementary varactor pairs to reduce the influence of the fabrication error. When the size of PMOS was increased, the capacitance accuracy of the MC level capacitor array was improved. Finally, a low complexity, wide tuning, high precision all-digital controlled LC oscillator was designed.(3)Based on 180 nm CMOS process, the proposed all-digital controlled LC oscillator was designed. The simulation results show that minimum capacitance value of the new structure was 7.42 a F. The frequency range of the all-digital controlled LC oscillator was 3.2 to 3.8GHz. The output voltage swing was 1.75 V. The phase noise of the 3.5GHz signal was-120 d Bc/Hz at a 1MHz offset. The FOM value was 211. The accuracy of frequency modulation was improved while the FOM value, phase noise and power consumption was kept at the same level.The above work will be a reference for the design and research on the DCO based all-digital phase-locked loops and all-digital single chip wireless transceivers.