Development Of The Control System Of Micro And Nano CT

As the development of technology and manufacturing procedure are getting improved everyday, the internal structure of certain object is getting increasingly sophisticated. As a result, it is required that the industrial CT must be equipped with higher accuracy. Micro and nano CT can achieve non-destructive three-dimensional image of small samples, the resolution of which can reach as accurate as tens of nanometers. It can be applied in all field where accurate processing is needed. In order to satisfy the requirement, this paper tries to offer a solution with a micro and nano level CT core controller, which is equipped with higher accuracy and speed. This solution can organize different parts of the CT to work with certain order, including an electronic scanning X ray source with powerful and nano level focal point, a flat detector, a precise mechanical platform and a image reconstruction system. Therefore the whole system can get a reconstruction image with better result, which can lead to higher accuracy and speed.This paper studies the solution of micro and nano CT control system. With dual core processors of FPGA and DSP as the core controller of the embedded system, it forms a distributed control system with hierarchy. The dual core processors not only make the DSP high-speed data processing function well, but also make full use of the high design flexibility of FPGA. In addition, this paper not only completed the function of data transmission between DSP and FPGA, but also finished the function of compensation, where the data are processed in DSP with short reference method and transferred to host computer for reconstruction. With this function, the solution offers an effective way to achieve nondestructive measurement with higher accuracy and speed.For the part of hardware, the system chooses DSP as the main controller, which is TMS320F28335 from TI company. The system also chooses FPGA as the Deputy controller, which is EP2C5Q208 N from Altera company. What’s more, an SRAM is chosen as the external RAM of FPGA. For the specific control interfaces of X-ray source and detector, it includes 2 RS-232 interfaces and 7 special control interfaces; 16 general input and output interfaces; motion control interfaces, including 3 RS-232 interfaces; finally, the host computer communication includes 1 RS-232 interface.For the part of software. At first, the mode, logic and process of the scanning in core controller are analysed and realized. It adopts the top-down design in FPGA. With Verilog HDL language for programming, it completed the serial communication between core controllers and the host computer, as well as between core controllers and peripheral equipment. It also completed the logic design of FPGA dual port RAM and water light for running indication. All the compilation, synthesis and simulation are completed in the Quartus II9.1 software. For DSP, it adopts the DMA to finish the data communication of inside RAM in FPGA. What’s more, it also finished the control function with the outside interrupts of DSP. All the compilation, synthesis and simulation are completed in the CCS4.0. For the compensation algorithm, it is implemented on MATLAB with the method of short reference compensation to achieve X/Y deviation fitting. In conclusion, it is achievable to compensate geometric deviation with the method of short reference. At last, the function test is performed at the hardware platform.For function test, the speed and accuracy of data transmission between DSP and FPGA communication are measured. The highest transmission speed can reach 43 Mbps, while the accuracy rate of transmission also reached as high as 100%. Through the method of short reference compensation, a higher resolution image is achieved, which means higher accuracy. The system works well as expected.