The Design And Implementation Of A RICS Processor Performance Model

At present, the processor design is becoming increasingly complex, how to efficiently design a processor in a limited time is becoming an important issue. Architecture simulators are popular tools in the processor design process. In this paper, we have analyzed the feature of a RISC processor, and developed its performance model based on the GEM5 simulator, and evaluated its performance using the standard SPEC test program.In this paper, the main contributions and innovation points are as follows:1. We have simulated the RISC processor pipeline and functional units in detail, including branch predictor, register file, reservation station, register dependence, memory dependence and multiported cache.2. Increasing the complexity of branch predictor a nd adding more ports for cache could promote the performance of the processor. Experiments result shows that, tournament predictor, which combines the global branch predictor and the local branch predictor, promotes the processor performance by 6.5198% in contrast to the global branch predictor. Compared with the real multiported cache, the banked cache implemented by a pseudo multi-port cache loses 1.64% performance.3. Optimizing the physical register file organization and the Tomasulo algorithm could also promote the performance of the processor. The physical register file could be composed of 32-bit registers or 64-bit registers, and the performance of 32-bit register outperforms the 64-bit register 0.20%. Compared with the central Tomasulo algorithm, the distributed Tomasulo algorithm has less IEW(issue, execute and writeback) blocking, and 2.55% performance improvement has been observed.