The Optimization And Implemention Of Stream Architecture Simulator

With the continuous development of VLSI technologies, CPU design became more and more complicated. Software simulation allows designers to use high level programming languages (C/C++) or specific hardware description language (VHDL, Verilog) to construct the processor architecture, and to conduct simulations on functionality and performance. By doing software simulation, processor architecture prototype can be implemented and evaluated in small amount of time. As a result, this technique has been widely adapted during the early stage of processor design.The purpose of this paper (thesis) is to optimize the stream-architecture simulator based on X processor. The first three chapters briefly describe the hardware prototype of this simulator– X processor, and the basic design concept of this simulator. The following two chapters explain the design optimization work in detail. Performance evaluation and comparison between the before/after the X processor design is done in Chapter 6.In Chapter 4, two different optimization methods are presented to speed up the simulator. Using a special technique named"Indirect Threaded", the first method speeds up the kernel-level modules of the simulator. In original design of X processor, instruction modules are divided/partitioned based the functionality of functionality."Indirect Threaded"puts all instruction modules at the same level and executes them sequentially, which reduces the hardware overhead and improves the simulation speed. The second method speeds up the simulation by using rough estimation instead of explicit computation on non-critical blocks. During early design stage, correct functional behavior instead of exact data result (timing, power, etc.) is expected, hence we can use fast estimation on time-consuming blocks without losing the precision of circuit functional behavior simulation.In Chapter 6, three aspects of the critical performance evaluation/comparison are presented. Kernel-level performance consists of usage of kernel-level modules and stall-cycles. Steam-level comparison consists of stream-level instruction numbers, data transfer of SB, and I/O address tracing and intercepting. The statistic data of I/O is presented individually at the end of this chapter to characterize the stream-based I/O.From the simulation result, we can see that the simulating speed of X processor reaches 269K-cycle/second. The overall performance increases 23.8% compared to original X processor architecture.The work of this paper was funded by National 863 research projects (2005AA110020) and Most-Important projects of PLA. The actual algorithm of this work has already been adapted in many engineering works.