Research On The General Reinforcement Mechanism Of Fpga-based Space Network Processing

With the rapid development of semiconductor technology, the appearance of VLSI makes the utility of the electronic systems in the field of aerospace more widely. Due to the advantages of the short design cycle, the high configurability and the high performance, FPGA has become a key component in the space-based systems. However, as the device size becomes more and more smaller, the noise margin is also gradually reducing and the chips become more sensitive to the effects of a single particle, which have seriously affected the system.In recent years, because the adverse effects of Single Event Effects are constantly enhancing, the demand of the reliability of space-based systems has become increasingly high. The method using redundant protection circuit fault tolerance to improve the reliability of the systems which is based on high-performance commercial FPGA chips has become a trend. Network processing is characterized by a large amount of data, the obvious distinction between the control processing logic and the data cache and the relatively fixed operating procedures, etc., so the traditional reinforcement method lacks specificity to the space-based network processing. In this paper, we propose a general reinforcement mechanism based on researching the FPGA-based space network processing reliability. The main work and innovations include the following three aspects:Firstly, this paper proposes general reinforcement mechanism SDCR(Separate Data and Control Reinforcement)for the space-based network processing based on FPGA. According to the characterizes of the space-based network processing, the data path and the control path are distinguished for reinforcement and the reinforcement methods are flexibly used. Use multi-mode redundancy to reinforce control process logic, and use the coding to increase reliability of data.Secondly, based on this general reinforcement mechanism, we have designed and implemented space-based network processing logic. Based on the operational principles of the Xilinx TMR tools, this paper proposes the module-level TMR reinforcement method with the modified function. The logic uses method of module-level triple modular redundancy, and the errors of important registers are corrected. It is more versatility and portability than the TMR tools of the Xilinx Inc..Finally, in order to test the reliability of implementation of space-based network processing logic, the fault injection test is made for the logic. Based on introducing the common reliability evaluation method and with the analysis of the advantages and disadvantages of two fault injection methods based on the bit stream files and the storage units, we choose the fault injection method based on the storage units as the reliability verification method. Propose automatically fault injecting and testing methods to achieve the multiple injection faults and the integrity of the measurement function. Fault test results show that the reinforcement mechanism is simple and efficient, with good reinforcing effect.In summary, this paper researches FPGA-based space network processing reinforcement issues, and proposes the SDRC, the module-level TMR with the correction function and fault testing programs, which have important reference value for space network processing reinforcement issues.