The Design And Implementation Of High Performance And Fault-Tolerant Support Last Level Cache

With the development of the application requirement and the chip design technology, Chip Multi-Processors(CMP) has become the mainstream processor architecture. Increasing the level of Cache and enlarging the capacity of the Last Level Cache(LLC) are the two general ways, used to alleviate the increasingly serious “Memory Wall” problem in CMP. However, the LLC is faced with several challenges, such as the growing of on-chip wire delay, the limited off-chip bandwidth, multi-threads interference problem, and the urgent reliability demand. How to design a LLC with the effective management strategies and the fault-tolerant support is of great significance.Matrix-M is a high-performance multicore DSP. The success of its research will have great importance to the fully autonomous strategy of the kernel chip in China. On the background of Matrix-M, this paper has implemented its LLC, especially the effective management strategy and the fault-tolerant support unit. The work and contributions are in the following:Firstly, we introduce the overall structure and memory hiberarchy of the chip, and analyze the design requirement of the LLC. According to the requirement, the data/tag bank structure, the replacement algorithm, the mapping rule, and the writing policy are determined.Secondly, three efficient management strategies of the LLC is put forward and implemented. 1) By injecting the priority into the traditional replacement algorithm, the data residing in the Cache has different preference, which can effectively alleviate the relatively poor locality problem of the LLC and reduce its miss rate. 2) Through the configuration of the addressing method in external storage space, the shared space and private space in the LLC is flexibly divided, which can improve the space utilization rate of the LLC. 3) A writing strategy called “False Hit” is presented on the basis of the writing policy, which can reduce the compulsory miss in the LLC. Experimental results show that the three kinds of management strategies improve the performance of the LLC in different degree.Thirdly, the fault-tolerant mechanism of the LLC based on Hsiao code is designed and implemented. The code implementing, error handling and data consistency processing are specially introduced. Synthesis and experiment result show that the software and hardware overhead of this mechanism can satisfy the design requirement.Finally, the verification and synthetic optimization for the LLC are carried on. Experimental results show that the design of LLC is correct, and achieves the convergence of the coverage. Under the 45 nm process of a certain manufacturer, the timing, area and power consumption can satisfy the design requirement.