The Research And Implementation Of Directory Controller In Multi-core Processors

Along with the enhancement of the computer application demand, the multi-core processor technology appeared, which compared with single processor has a high cost performance, can fully develop the parallelism of process, and has been widely used in various fields in real life. In the process of development of multi-core processors, Cache consistency poblem is the hot question in performance of multi-core processors, and Cache coherence protocol based on the directory(referred to "directory directory protocol") is a usual kind to solve this problem. However, with the development of technology of multi-core processor, the number of processor and the complexity of network grow quickly, lead to the cost of directory protocol increase gradually, to affected the performance of multi-core processor upgrade to a certain extent, so the efficient design and realization of directory protocol has the important theory and project value in multi-core processor technology, and directory the controller as the key part of the protocol based on directory has the important research value.According to the research of the Cache coherence protocol based on directory and the behavior rule of Cache at all levels under directory protocol, summarizes the working principle and working process of DCU which is the core components of directory protocol controller, and completed the design and implementation of DCU. In the process of design and implementation, this article fully considers the possible problems in the practical work of DCU, and find the corresponding solution.In order to avoid deadlock of the DCU, this paper do the work to avoid deadlock to.Each kind of consistency affairs have their own dedicated buffer, and increase the depth of the buffer appropriately. When the SnpBuf buffer without enough residua space to store the next snoop transaction, DCU will cease to produce new snoop transaction, and issue the not successful response to the transaction request, free the hardware resources.In order to poise the snoop requests, and avoid a single L2 Cache is frequent as data provider to snoop requests, which leads to the local processor waiting, in the design of DCU, each directory entry(DirEntry) is added a data provider identifier(F). Using the value of F to identify whether the corresponding L2 Cache as the data provider of snoop request, to ensure one L2 Cache won’t become a data provider repeatedly, so as to balance the snop load.In system, accessing the DirWay need 2 cycles, in order to enhance the access rate of DirWay, each directory way(DirWay) is devided into two single-port RAM, call them DirWayH and DirWayL respectively, and do intersection addressing for them.According to Index[6] in access address, each access request will choose one of them to access. According to the Spatio-temporal locality principle, the address of continuousaccess request may be adjacent(Index[6] values are differrent), continuous access will be sended to DirWayH and DirWayL respectively, so as to realize each cycle complete an access request.In the end of this paper, we do the function verification for DCU, the result says that DCU can execute all function correctly, acheive the goal of design.