Development And Optimization Of Plasma Etching For 40nm Polysilicon Gate

As one module of the strictest requirements in IC manufacturing process, 40 nm gate etching process faces many challenges, such as physical profile, through pitch CD bias loading, line width roughness and CD uniformity. This paper focuses on the above four aspects.Firstly, by changing process integration in gate loop, the loading of N-doped and P-doped gate profile is minimized. During different etching steps, the effects and mechanisms of oxygen, pressure, and physical bombardment are also investigated. Secondly, CD loading of through-pitch is reduced by adding plasma treatment step and bias power. CD variation is controlled within 2nm in key design pitches. Thirdly, line width roughness is optimized. The type of etching gas, plasma treatment technology and physical bombardment show different effects. Finally, by tuning temperature and pressure, gate CD uniformity is far better than the target.In this thesis, not only is 40 nm gate etching recipe developed which fully meets requirements, but also mechanism of action is proposed based on experimental results. It will be helpful for developing more advanced etch process in future.