Research And Implementation Of PRACH Receiving End Based On C-RAN Architecture

The traditional radio access network is high investment, high energy consumption and low utilization rate, so it has been encountered enormous challenges. Mobile operators have to find low cost method to provide users with wireless business. C-RAN is a green radio access network. It consists of centralized processing, cooperative radio and real-time cloud structure. It also can reduce cost effectively, improve the capacity of the users and meet the needs of future. Random access is the first step of user’s network access, so it plays a key role in C-RAN.Firstly, the overall architecture of C-RAN and the scheme of digital front-end based on C-RAN are studied in the thesis. Digital front-end system contains PRACH processing. The clock frequency is 250 MHz, the throughput of single antenna is 8Gbps, the delay is less than 1ms and the link supports 5MHz, 10 MHz, 20 MHz bandwidth. The function and physical channel structure of the PRACH in LTE are analyzed in the thesis, including the format of the leader sequence, the structure of time and frequency domain and the way of resource allocation.Then, the key algorithms of receiver in PRACH is analysed in the thesis, including the scheme for receiving and detecting. The direct FFT algorithm and time domain downsampling filter algorithm are studied. The complexity of the two algorithms is also compared. According to the floating point simulation model of the PRACH builting on the Matlab platform, the floating point simulation of the direct FFT algorithm and time domain downsampling filter algorithm is done. And the detection probability is compared at the receiving end of PRACH. Besides, the fixed-point simulation of the two algorithms is done in the thesis. The fixed error is about 410?.Finally, the overall architecture of the receiving end in PRACH is designed based on the digital front-end system of C-RAN. And the circuit of each module is detailedly designed. The thesis analyses the advantages and disadvantages of two kinds of filter structure. It also verifies the correctness of each module and analyses the resource consumption and performance. At last, the circuit is tested on the FPGA board. Through static timing simulation, the biggest clock frequency is 298.15 MHz. The throughput of single antenna is 9.54 Gbps. The delay of the circuit is 0.527 ms. And the circuit supports three different kinds of bandwidth. So it meets the requirements of the digital front-end of C-RAN.