The Research And Implementation Of Detection Technology In LTE PRACH

In recent years,along with the growing user demand for high-speed data services,digital mobile communication technology is in the rapid development stage.LTE as the most powerful commercial communication system,has a higher transmission rate,more flexible system bandwidth and lower latency.In the LTE system user equipment achieves uplink time synchronization via random access procedure.Therefore,the merits of the random access detection technology will directly affect the performance of the LTE system.This thesis focuses on TD-LTE system physical layer random access detection technology.First,the physical layer random access algorithm design and the simulation performance is given,then based on TMS320C6670 multicore baseband processor the design and code implementation for each sub-module is implemented,and the code is optimized by a variety of ways,so as to achieve the requirement of highly efficient real-time processing.The main works and innovations of this thesis include:1.The random access procedure in TD-LTE system is studied.And combined with the relevant provisions of 3GPP protocol for physical layer random access,the key technologies of PRACH is analyzed in-depth.2.A PRACH detection algorithm that has strong adaptability for mobility is proposed.Under the condition of AWGN or ETU channels and different preamble formats,simulation results show that either at low or high speed scene the performance of detection probability of the proposed method is at least 3dB better than the protocol requirement and significantly better than the conventional preamble detection algorithm.Because of the less time consuming,the algorithm has promising value in engineering.3.Based on Texas Instruments(TI)next-generation multi-core processor TMS320C6670 the design and implementation of PRACH receiver is given.In consideration of the accuracy and computing speed,a reliable fixed-point implementation is designed.At the same time to ensure the timeliness and the concurrency of the system,combining with the hardware architectural features of TI C6670,the design of PRACH sub-modules is completed.By given various optimization methods and verification of results,the feasibility of the system implementation is demonstrated.