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The Design And Implementation Of High Speed Transmitter Of 60GHz System

Posted on:2015-09-30Degree:MasterType:Thesis
Country:ChinaCandidate:W T ZhuFull Text:PDF
GTID:2308330473952821Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
With the wide spread of multimedia technology, there has been a increasing demand on wireless communications technology such as its bandwidth and rate. Since many countries and regions have gradually opened up a 7-9GHz bandwidth to be freely available in the 60 GHz band, which can provide more than Gbps transmission to meet the requirement of the proposed transmission rate of people. So 60 GHz millimeter-wave wireless communication system wins the focus of the academia and industry because of its advantages.Combining with a specific project, this paper designs and implements a high speed transmission link which is a part of the baseband development circiuit of Terahertz Communications Research.The baseband circuit provide implementation and verification platform for the Terahertz Communications Research. In this background, this paper studies the implement and test of the high speed baseband transmission circuit.The first chapter introduces the background and significance of the research firstly, and then introduces the history and development of the current development of the 60 GHz technology.The second chapter introduces the standard of the 60 GHz system-IEEE 802.11 ad, and gives a brief introduction of the physical frame structure, Gray sequences, modulation and coding. And then introduces the various devices used in the project, including SDRAM, FPGA and DAC.The third chapter which is the focus of the paper, introduces the general framework of the transmitting end of the 60 GHz system at first, and then describes the implemention of the SDRAM controller, and then introduces the process of framing. It also analysis the structure of the shaping filter and shows how to quantify the coefficients of the filter. Two different ways to implement the filter are introduced. At last the process of debugging the DAC sub-board and the program of interface to DAC are described.The fourth chapter describes the verification of each module and compares the resource’s consumption of the two methods to implement the filter.The fifth chapter concludes the paper and introduces the main contribution and shortcoming of this paper.In the end of the paper the future work of the 60 GHz is prosepected.
Keywords/Search Tags:60GHz, SDRAM, DAC, Shaping filter, FPGA
PDF Full Text Request
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