A High Speed Interpoloted /Averaging ADC

ADC is the link between the analog world and the digital world and is the key part of most of the mix signal systems. Different system has the different requirements on the resolution and the speed of the ADC. For example, high speed and the low to middle resolution ADC is the key part of the ultra wide band(UWB)、disk driver and optical communication etc.Although the multi-channel ADC can realize very high speed, it costs much hardware and usually need complicated back-end calibration, so we usually combine Flash ADC with interpolation ADC to realize the design of high speed or the ultra high speed ADC.The paper firstly introduces the research background and the significance of the this work. Then it describes the development of the ADC, and introduces the theory and characteristics of the different ADC. Besides, it introduces the theory and design of the Current Mode Logic(CML) circuit, which is widely used in the design of high speed and ultra high speed ADC.After the theoretical research of the high speed ADC, it introduces the design of a 4bit 6 GSPS resistor interpolated ADC in detail,including the design of the pre-amplifiers,the comparators and the encoder. The whole circuit of ADC widely uses differential circuits and CML circuits. After the design, the sub-modules and the whole circuit are simulated by the process of TSMC 65 nm with the software of HSPICE. Finally the layout and post simulation are completed to verify the design further.Post simulation shows that the range of the DNL and INL is-0.1 LSB~0.18 LSB and-0.377 LSB~0.227 LSB respectively without the digital calibration, when the sampling speed is 5 G, so the resistor averaging and the matched technology of the layout have achieved good results. The ENOB of the ADC is around 3.5 bit as the frequency of the input signal varies. As a conclusion, the ADC has a good performance of both static parameters and dynamic parameters.