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Research And Implement On NBI Suppression Technology Of Direct Sequence Spread Spectrum

Posted on:2015-06-24Degree:MasterType:Thesis
Country:ChinaCandidate:T LiuFull Text:PDF
GTID:2308330473950336Subject:Electronic and communication engineering
Abstract/Summary:PDF Full Text Request
Direct Sequence Spread Spectrum(for short, DSSS) system is widely applied in modern communication field for its anti-interference ability. But its anti-interference ability is limited because of the limited available bandwidth and system complex. Once the power of interference exceeds the jamming margin, the DSSS system will get a poor performance and even malfunction.The Narrow Band Interference(for short, NBI) Suppression technology in DSSS system is studied and implemented in this thesis. In detail, the thesis designs an NBI suppression scheme applied in DSSS system with triple channels, implements the DSSS NBI suppression software based on the FPGA platform, tests and analyzes the function and performance of the software. The main contributions of the thesis are as follows:Firstly, an NBI suppression scheme based on Code-Aided technology is designed to be applied in DSSS system with triple channels.(1) The thesis verifies the relationship between NBI suppression performance andpackage length M in Code-Aided algorithm, and determines M =12 tomeet engineering implement needs;(2) A delay path scheme is introduced into Code-Aided algorithm. Compared totraditional algorithm, the new algorithm improves the performance of NBIsuppression by 0.6 dB/Hz with few system resources increasing;(3) The Partial Updating RLS algorithm is applied to design an architecture whichthe autocorrelation matrix updating module is shared by triple channels. Thenew architecture has the same performance with those common architecture(Every channel possesses a matrix updating module independently), butreduces resource consumption by about 60%.Secondly, a top-down NBI suppression software applied in triple channel DSSS system is designed based on FPGA platform. And some details are given out in this thesis, such as the overall framework, module partition, I/O and constrains, and the main process of some important sub-modules.At last, the performance of the NBI suppression software is tested and analyzed in detail. The testing results show that: firstly, the software realizes the controlling function of RF gain and output power gain; secondly, in the worst cases(0C N =56.5 dB/Hz, toneJSR =34 dB, NBIJSR =27 dB), with the help of NBI suppression software, the lost 0C N(carrier to noise ratio) of DSSS system is less than 2.5dB/Hz; and so, the system satisfies the specification: bit error rate of I branch is less than 81.0 10-′, bit error rate of Q branch is less than 71.0 10-′.The NBI suppression software designed in this thesis, located at the front of DSSS receivers independently, doesn’t affect the structure of existing receivers, so it has a good portability and practicality in current DSSS systems.
Keywords/Search Tags:DSSS, NBI, Code-Aided, FPGA
PDF Full Text Request
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