Design And Realization For DSSS Modulator/Demodulator Based On FPGA

The spreading spectrum(SS) communication system has stronger ability of resisting narrow band, multipath and jamming interference than that of the conservation communication systems,and it also has the characteristics of low probability of intercept and multiple access secure communication. Nowadays, the SS technology has gotten rapid progress. This thesis primarily discusses the baseband processing of DSSS communication signal based field programmable gate array (FPGA) ASIC chip. The design technique of FPGA related to SS communication system also has been discussed in this thesis. Finally, the related subsystem has been designed and implemented based on the FPGA development platform Quartus II5.0 belonging to the Altera Company.The total system can be divided into two parts, i.e., transmitter and receiver unit. The transmitter unit mainly consists of the serial-to-parallel conversion, differential encoder, PN code generator and QPSK modulator and so on. The receiver unit mainly consists of the digital down converter, spread spectrum demodulator, differential demodulator and so on.Firstly, the thesis introduces the characteristics of the SS communication system and the development related to SS technology at present in the world. The outline and the research idea of the thesis also have been introduced.Secondly, some algorithms of narrowband interference resisting, PN code and carrier synchronization are presented in this paper. Through practical demand, an algorithm of a digital receiver of DSSS with zero-intermediate frequency is put forward. Narrowband interference resisting algorithm, PN code acquisition and tracking algorithm, carrier demodulation algorithm are described. It resists the narrowband interference by using the digital adaptive heterodyne filter at the forint end. It improves function of PN code synchronization by double threshold series acquisition and time division multiple single correlator tracking. It reduces the complexity of carrier withdrawing algorithm by using soft costas PLL based on sign function. The structure can be easily expanded by using the improved CORDIC algorithm in the implementation of the NCO.And then, the analysis and the implement detail for all modules based on Quarus II5.0, both transmitter and receiver unit, have been given in this section. The results of behavior simulation of all modules also have been represented. The hardware design of the whole system and the test results in the system are presented in the paper. It is seen that the system has stable performance, high activity, small size, and can be easily produced and flexibly updated. It is also fit the demand of the system.The summaries of the thesis and the possible extensions and improvements based on the completed system have been represented at last.