Research And Implementation On Node Gain Control And Frame Synchronization Scheme Of CRAHN Network

CRAHN(cognitive radio ad hoc networks), as a distributed cognitive network, combines cognitive radio technology and Ad-Hoc network. It enables the user to switch between the spectrum holes freely. And it has the ability to transmit voice、 image、 video and other broadband data and CRAHN caters to communication in emergency.In CRAHN network, the near-far effect caused by the head of each constantly moving cluster may lead to the loss or the distortion of the frames of the OFDM receiver. In poor channel conditions, the frames may be unsynchronized or wrongly estimated that a frame signal is coming. This paper focuses on the algorithm improvement for gain control and frame synchronization technology of receiver in the CRAHN network.Firstly, the paper introduces the causes of CRAHN network in the near-far effect. More application of logarithm amplifier in the closed loop gain control system is involved in this paper. Results prove that in the system with a logarithmic amplifier, the setting time of automatic gain control has nothing to do with the input signal. Therefore, this paper uses the variable gain amplifier AD602 and the logarithmic amplifier AD8310 to design an automatic gain control system whose dynamic range can achieve 80 d B.Secondly, the paper studies the frame synchronization algorithms of OFDM receiver in different channel conditions. This paper analyses and simulates the SC algorithm and SC algorithm in time domain based on PN sequence. The SC algorithm is simple but it can’t find the precise frame synchronization point. The SC algorithm in time domain based on PN sequence can find the precise frame synchronization point, however, the algorithm consumes a large number of logical resource in hardware realization, which is not infeasible for FPGA implementation. Therefore, this paper synthesizes these two algorithms to put forward a kind of improved SC algorithm in time domain based on PN sequence and simulates it. The simulation results show that the algorithm can save the FPGA hardware resources. Through the FPGA simulation, it can accurately capture burst frames.Finally, on the Quartus II platform, this paper uses the VHDL language to implement SC algorithm in time domain based on PN sequence proposed in this paper and captures the data with Signal Tap to verify the results. And test and verify the hardware in the FPGA/ADC/DAC hardware module...