Research And Process Development Of Planar Optical Waveguide Attenuator

With the rapid development of broadband metropolitan area network(BMAN), DWDM(dense wavelength division multiplexing) is widely used. It becomes clear that an important application prospect in the field of optical communication and the huge market potential, wide attention has been given to the electrically controlled variable optical attenuators for its remote and real-time characters. For example, optical attenuators are used between stages of EDFAs to balance the gain spectrum. In WDM systems, optical attenuators are used to set signal strength within the range of a receiver, otherwise the bit error rate of data transmission will increase.In this paper, I studied the design and process of electrically controlled variable optical attenuators which based on silicon micro processing mainly, the working is mainly divided into three parts:1) Based on the research of different design structure in the variable optical Attenuator field, according to the situation of our factory, put forward the best product design with directional coupler and Phase-shifter structure.2) Before the sample production, I studied some key process, such as Inductively Coupled Plasma etching, BPSG deposition process for upper cladding layer and Ge-SiO? process for core layer. Through making experiment on the key parameters affected process condition again and time, compare the results. Finally the optimal process conditions is found, which meet the demand of design completely, it makes the key technical parameters of the product can meet the design requirement well. For the smooth production has laid a solid foundation of the sample.3) The test result is analyzed. Given a further analysis of the causes of the failure Samples from two aspects included process and design. And through the comparison test to find the key factors influencing the device performance, and give an adjustment on the design and process in time, and major product charactes, such as IL is lower than 1db, and PDL can be controlled around 0.6db. ultimatly the device performance basically meet the design request.