Research And FPGA Implemention On Burst OFDM Synchronization Technology

In recent years, with the development in a high speed of the IP technology in the Internet Protocol Version 6 core network, more and more wireless communication systems have the character of burstiness. Meanwhile, The Orthogonal Frequency Division Multiplexing(OFDM) technology has been widely applied in many wireless communication systems as its strong anti-multipath interference and high spectrum efficiency. However, because of the sensitivity to synchronization deviation, symbol Interference(ISI) and Carrier Interference(ICI) can be caused by subtle deviation in OFDM systems.Based on the study of OFDM synchronization theory, a new OFDM joint time-frequency synchronization algorithm is proposed in this paper. In detail, the paper’s main work and innovations are as follows:Firstly, a new frame synchronization algorithm, which revises traditional timing metric function based on the PN sequence is proposed, the proposed algorithm can be able to not only reduce the False Detection Probability(FAP) and Missed Detection Probability(MDP) effectively, but also eliminate the "platform effect" in the Schmidl frame synchronization algorithm(SC algorithm), because of having a very sharp correlation peak.Secondly, the fractional frequency offset algorithm is improved by combing Cyclic Prefix(CP) with Least-Square(LS), which take full advantage of Cyclic Prefix algorithm, consequently, the fractional frequency offset precision and the anti-interference has been greatly improved.Thirdly, the integer frequency offset estimation algorithm is optimized. As a result, the improved algorithm only needs one training sequence data, by searching the maximum in frequency domain, to estimate the offset. Which increase the efficiency of data transmission as well as the precision of frequency offset estimation.Finally, the implementation of the OFDM joint time-frequency synchronization scheme based on FPGA is introduced in this paper. The studying in this paper focus on not only simplifying the proposed synchronization algorithm and improving the efficiency of FPGA implementation, but also ameliorating the data structure to balance the FPGA logic resources and computing the rounding offset. Furthermore, to achieve the validity of the scheme, the results of simulation using both Matlab and Modelsim are given in this paper.