Research On Downlink Synchronization Technology And FPGA Implementation Of OFDM System

OFDM is a multi-carrier modulation technique,which has the advantages of high spectral efficiency,large system capacity,strong performance of against fading and multipath jamming.Because of the OFDM modulation needs to carry on the IFFT and FFT operation,and the subcarriers are orthogonal,therefore the OFDM system is very sensitive to the frame synchronization and the frequency error.Synchronizaion errors can greatly reduce system performance.Therefore,research on synchronization technique for OFDM systems is necessary.At first,the timing and frequency synchronization method for OFDM systems were studied in the paper.The first part of this thesis is the introduction of the research background,the research status,and the summarize of the synchronization and carrier frequency synchronization algorithm.The effect of synchronization error on OFDM system is analyzed in this paper.And then,the performance of several frame synchronization algorithms including the S&C algorithm,the conventional cross-correlation algorithm and the M-part algorithmis analyzed by simulation.Performance of carrier synchronization algorithms,including the moose algorithm and the time maximum ML estimation algorithm is studied in this paper.Finally,the M-part algorithm and the time maximum ML estimation algorithm are determined as the time-frequency synchronization algorithm in this paper.Another research work of this paper focus on the implementation of the time and frequency synchronization algorithm based on FPGA.In this paper,methods of frame synchronization,frequency offset estimation and compensation based on FPGA are discussed.In frame synchronization,not only introduces the module interface and function and the internal signal timing,but also expounds the threshold determination method and peak detection algorithm under different SNR.The design method of DDS is discussed in detail in frequency offset estimation and compensation.At last,the timing and function of each module are validated on the platform of the verification based on MATLAB and Modelsim.In the platform,the error and resource consumption are analyzed.This design obtains the good timing through the pipeline operation and the clock domain data processing,also has reduced the system resource consumption through the resource sharing.