Research On STAP Implementation Technology Based On FPGA

Space-time adaptive processing(STAP) algorithm can effectively suppress noise and interference. After forty years development, the research on basic theory of STAP algorithm has been mature, at present its engineering application is one of the main research direction in this field. And the key process to STAP implementation is the real-time computation of adaptive weights. In recent years, the Field Programmable Gate Array(FPGA) technology has been widely used in the field of digital signal processing. Therefore, this paper will focus on the implementation technology of STAP algorithm and its weights calculation based on FPGA.The main work includes the following aspects:1. A non-root algorithm based on QRD_MGS to compute STAP weights is proposed in this paper. Modified Gram Schmidt QR decomposition algorithm(QRD_MGS) is used to avoid direct estimation of covariance matrix and its inversion calculation. The traditional method based on QRD_MGS for solving STAP weights has redundant root operation. In order to avoid this shortage, a non-root operation algorithm is presented in the paper and its detailed derivation is shown. After deformation of original upper triangle matrix, each element of new matrix can be expressed by non-root value of original element.Therefore, the method avoids root operation. When compared with the original method, the improved way avoid the root operation, reduce the division calculation, and improve the precision of result, at the same time, it is more suitable for real-time hardware implementation.2. The implementation technology based on FPGA for non-root QRD_MGS algorithm is studied. The parallelism of the algorithm is analysed deeply. And the process is divied into five steps.In order to minimize latency, a strategy based on task partitioning is developed, which divid each step into some small tasks.And these taskes can work in pipelin.Therefor, the design can reduce latency.For the method, a parallel mapping struchture is exploited and implemented on FPGA.3. The implementation technology based on FPGA for computing adaptive weights with substitution algorithm is studied. After deeply analyzing the process of substitution, its inherent parallelism is developed. According to the deferent timing characteristics of input data, deferent parallel computing structure is designed.The forward substitution structure has the advantage of covering the clock overhead of matrix decomposition and the backward substitution can saves the multiplier, adder and other hardware resources by adopting local parallel strategy.4. A mapping scheme on FPGA for dimension-reduced STAP algorithm is designed. After deeply analyzing the process of STAP algorithm and its inherent parallelism, the process is summarized to five steps. For each step, the local parallelism is developed. A partial parallel and global pipeline mapping strategy and its multi-FPGA implementation architecture are designed.The design improve the execution efficiency and fully develop parallelism in space and time.