Research And Implementation Of Digital Background Calibration Technology For Multi-channel SAR ADC

Analog-to-Digital Converter (ADC) plays an important role in modern electronic systems, such as radar communications, image capture, video monitors, etc. Through the continuous efforts of academia and industry for many years, the ADC’s performance has almost reached the limits of the existing craft and current design level. In order to improve the speed of ADC to meet growing performance requirements, a multi-channel Time-Interleaved ADC (TIADC) has proposed and quickly gained a large amount of research.Theoretically, the speed of multi-channel Time-Interleaved ADC can be linearly improved by adding sub-channels. But due to technology mismatch (mainly consists of offset mismatch, gain mismatch and sampling time mismatch) exists between each channels, the performance of TIADC seriously decreased. In this thesis, digital aided design technology has proposed. By using digital calibration technology, the mismatch will be estimated and calibrated in digital domain.By studying the existing calibration algorithm, this thesis pointed out the shortcomings and proposed new calibration algorithms:offset mismatch calibration algorithm based on index average, gain mismatch calibration algorithm based on weighted integral algorithm and sampling time mismatch calibration algorithm based on statistical feedback method. Compared with conventional calibration algorithm, the presented calibrations in this thesis have low hardware resource consumption and no restriction on the input signal frequency, and high calibration accuracy.In order to verify the effectiveness of the calibration algorithms, this thesis built multiple platforms to do this work. Firstly, this thesis built four channel 4GHz 8bits multi-channel time-interleaved SAR ADC model in matlab/simulink platform and completed behavioral-level verification of the algorithms; Secondly, implemented the algorithms in verilog and completed the pre-simulation by modelsim, then compiled the algorithms by using TSMC 65nm technology and completed post-simulation; Also this thesis verified the algorithms in FPGA by using Altera Stratix IV platform. Combining the verification results of multiple platform, the calibration algorithms proposed in this thesis to be proved effectiveness in calibrating mismatch error between TIADC’s each channels.