The Study And Design Of All Digitally Controlled Clock Generating Circuit

In recent years, semiconductor technology is developing rapidly, which result in the large development in the field of wireless communication system, these developments have brought much changes and convenience to the people's life.In the wireless communication system, the clock produced circuit is an indispensable part, and at present,most clock circuit are produced by PLL (Phase lock loop) frequency synthesizer, but this need to use a crystal oscillator to provide reference clock signal.But with the semiconductor process come into deep submicron CMOS process, the integration of the system is required more and more high, however, crystal oscillator cannot be SoC integrated, this will cause great influence to the system's total area and cost. Point to this phenomenon, combined with the working theory of the digitally controlled oscillator (DCO), which is used more and more in the wireless applications, the paper put forward a new idea--All integrated digitally controlled clock generating circuit.The most center part of the All Integrated Digitally Controlled Clock generating circuit is the digitally controlled oscillator, The DCO can generate a corresponding oscillation signal via using a frequency-control-word (FCW) transfered from a flash memory, this oscillation signal can be converted into a clock signal through using a divider. According to this theory, the paper has established a model in behaviour level in the Simulink of Matlab, and then simulated the model, obtained some simulation waveforms. The model in this paper, we can obtain a resolution of 100Hz with an digital dithering technique.Though the paper is just made a systematical simulation for the new digitally controlled clock generating circuit, but from the simulation result, we can verify the idea of the All Integrated Digitally Controlled Clock Generating Circuit is workable, it can put into practice and be used in the actual circuit.