A Study And Design Of 10bit Unary-R-2R DAC

As a convert from digital signal to analog signal, DAC is one of the key part of signal processing systems. Current steering DAC is the main structure of the high speed of DAC, it is widely used in multimedia and communication. With the rapid development of mobile devices, the requirement of low power consumption and performance is growing higher. However, matching of current source in current steering DAC when working under minimum is becoming worse, leading to a decline in the performance of current steering DAC. In unary-R-2R DAC, LSB currents are generated by R-2R ladder. It kept current sources working with high current, relaxed the matching of current sources.At first, this paper introduced the development of DAC, briefly compared the structure and working principle of most kinds of DACs. Then deeply introduced the structure of unary-R-2R DAC and built the behavioral model of the DAC by MATLAB. After that, analyzed four actual circuit factors: resistance mismatch, current source mismatch, finite output impedance, RC delay. Researched these four factors through simulation platform. Results showed that finite output impedance affects the performance of DAC most.At last, designed the unary-R-2R DAC circuit under TSMC 0.13μm 1P8 M CMOS process, and simulated the whole circuit. The circuits included reference, current source, R-2R ladder. By using bandgap technology, reference generated a accurate reference voltage and turned to reference current. Current sources using cascode structure to suppress the affection from finite output impedance. R-2R ladder decreased the mismatch between each R by combination of multi resistance, to maintain the DAC static performance. Simulation results showed that max DNL and INL of the design are less than 0.5LSB. At 20 MHz input signal frequency and 300 MHz sample frequency, DAC SNR is 65.8d B, SFDR is 62.32 d B, ENOB is 9.7533. Design reached the requirements of 10 bit DAC.