Research And Design Of FIR Filters And FFT Processors For DC-OFDM Wireless Communication Systems

Ultra wide band (UWB) systems supporting data rates of hundreds of Mb/s are very suitable for the application to short range wireless communications because they can share frequency band with existing narrow band systems. One of the candidate schemes for high-speed UWB physical layer is dual carrier orthogonal frequency division multiplexing (DC-OFDM), which is adopted by the China-Wireless Personal Area Network (C-WPAN) working group in 2011.This thesis has conducted studies on high-throughput FIR digital filters and FFT processors for DC-OFDM wireless communication systems. This paper starts from algorithm study and system modelling and architecture analyzing and hardware design to circuit simulation, function verification and synthesis.This thesis proposes new structures for parallel finite impulse response (FIR) filter. With new polyphase decomposition methods, all the subfilters in the proposed structures contain symmetric coefficients, then every subfilter only needs half the number of multipliers. The total number of multipliers is then reduced at the expense of additional adders. This design is implemented with TSMC 65nm technology. Synthesized result shows that the area of the proposed 2-parallel structure is reduced by 23%, the area of the proposed 3-parallel structure is reduced by 12%, when compared to the existing FFA structures. Proposed FIR digital filter is applied to UWB wireless channel simulation.This thesis presents an 8-parallel FFT processor for DC-OFDM system. Architecture parallelism associated with FFT decomposition is used to explore the power-area space. Also, radix factorization is investigated for a given FFT size. A mixed radix algorithm is proposed to realize 128 point FFT computation. An Eight-Path Delay Feedback (EPDF) structure is proposed to implement this algorithm. Finally, a modified twiddle factor multiplier is adopted to further optimize this design. The proposed FFT processor is implemented using 0.13μm CMOS process with a core area of 1.44mm2. The throughput is up to 1GS/s, and the power dissipation is 39.5mW when working at the throughput of 500MS/s. This design has reduced area and power compared with other existing 128-point FFT processors.