Key IC Design Based On Near-Zero-V_T MOSFET

Micro-nano-electronics under ultra low voltage is the edged research areas for contemporary academic and industry fields.In order to design sub threshold in millivolts range, I will utilize two primer methods of large width and length ratio(LWLR) and bulk biasing, and the future focus be on the fuse of the above two.Supporting by Jiangsu Province Nature Science Fund(BK20141196), I finished works in two factors as: 1) to review the silicon limit’s supply voltage and the analog design paradigm in Micro-nano-electronics under ultra low voltage, 2) to model for building novel key analog circuits in less MOSFETs with LWLR tech from single to double to triad “tubes” concerning drain currents.Focused on Lee’s Circuits[1] coined triad trigger topology, this thesis includes two blocks as 1) to construct I-V characteristics of n- and p- MOSFETs, 2) to apply these formulae into modeling of CMOS NOT and 3MOSFET, 3) in brief bulk biasing approach was also trained and compared with CMOS NOT-based filters(low-pass and band-pass).The key results of our trained or invented circuits show that the power supplies be 1) 500 m V for CMOS NOT-based filter, 2) 100 m V for 3MOSFET; and the bi-threshold formulae contained 3) six parameters with errors less than ten percents.To push forward the healthy development of Brain Health Microelectronics, above works may contribute solid blocks for new house of green IC designer.