Design Of NOC-based MPSoC With Distributed Memory Architecture

The advancements in nanometer technology have allowed to integrate several embedded processors on a single chip creating multiprocessor systems-on-chip (MPSoCs). The MPSoCs are proved as a promising solution to meet the increasing performance requirement of real world complex applications. The communication demand of processors is fulfilled by Networks-on-Chip (NoC) that are efficient and a scalable alternative over shared buses. MPSoC on Field Programmable Gate Arrays (FPGAs) is a new and increasingly important trend. These days several FPGA-based MPSoC are appearing. These facilitate rapid prototyping and allow for research in new architectures without the worries of their ASIC production. In Multi-core Network-on-Chips, espe-cially for medium and large scale system sizes, memories are preferably distributed, featuring good scalability and fair contention and delay of memory accesses, since the centralized memory has already become the bottleneck of performance, power and cost.In this dissertation, it shows a Data Management Engine system on Zedboard FPGA, based on the research on NoC-based MPSoC. And it solves the problem about communication and synchronization between muitiple processors.4 MicroBlaze processors and 1 Cortex-A9 dual-core processors are used. The system consists of Time Stamp Unit, Synchronization Unit, Data Movement Unit, FIFO-based Communication Unit, Memory Access Unit, Switch, MicroBlaze Interface and Network Interface. Every processor can send data from local memory to others or access sources in other nodes. Time Stamp Unit stamp every data with current time to ensure the data will not be overtime. Besides, the API programs are developed to faticitate using the hardware. Users can use the system easily after reading the manual of API primitives. Every modules in the system are simulated in NC-Verilog, and the results show that the designed circuits meet the design target. Similarly, each API primitive is tested in Xilinx SDK, and the results show that the designed circuits meet the design target.