A Study On Chip Level Failure Analysis Of Trench MOSFET

Trench Metal-Oxide-Semiconductor Field-Effect Transistor (Abbreviation MOSFET) is the priority choice of medium and low voltage power device for power applications. The structure feature is embedding gate into the trench region of the device.The article talking about the study on chip level failure analysis of Trench MOSFET, it mainly focuses on the complete failure analysis process and advanced analytical techniques and methods, providing failure mechanism analysis on various failure phenomena, showing improvement programs.1. Polysilicon residue induce Igs short, failure mechanism is when the polysilicon etch machine is operating, particle falling from the chamber, blocking etching polysilicon, polysilicon residue is formed, and bridged the source contact which on the same location. The improvement program is to add monitor frequency after wafer etching, and to tighten particle specification.2. There are some failure phenomena induce Ids leakage, one of them is discolor found on chip edge, failure mechanism is photo resist peeling on source implantation step, to form additional implant layer, resulting source shorted with drain. The improvement program is to extend coating HMDS time to prevent photo resist peeling. 3. Lattice dislocation induce Vth leakage, failure mechanism is the growth of Electro-Static Discharge oxide film by high-temperature furnace tube induce lattice dislocation. The improvement program is to grow the oxide film by low-temperature furnace tube.4. There are some failure phenomena induce low BVDSS, one of them is Aluminum spiking, failure mechanism is the titanium/titanium nitride barrier layer uniformity is poor, when depositing aluminum, aluminum drill the loose place, and reaction with silicon to form alloy. The improvement program is to grow the barrier layer by metal organic chemical vapor deposition.5. Contact lithography shift induced RDs(on) out of specification, failure mechanism is contact lithography shift induce self-aligned ion implantation offset, two MOSFET Ros(on) have change, resulting total chip RDS(on) failure.The improvement program is to optimize lithography conditions, and to reduce offset lithography specification.Split Gate Trench MOSFET (Abbreviation SGT MOSFET) is an advanced device which is based on Trench MOSFET. There is more polysilicon process than normal Trench MOSFET. The article studies on failure analysis of SGT MOSFET in research & risk run phases, the main failure mode is Igs short. 1. Failure mechanism of gate polysilicon residue is there is some lateral etching when wet etching removing oxide layer, resulting the same position gate polysilicon etching is not enough, and there is some residue bridging source contact. The improvement program is to reduce the photo mask overlay of source contact and source polysilicon link-up area, and to shorten the length of source contact.2. Failure mechanism of trench mesa damage is the trench film over etching, and silicon of mesa corner is exposed. When source polysilicon etching, the exposed silicon surface also is etched, inducing trench mesa damage. The improvement program is to delete the process of first sacrifice oxide, and to reduce SiN over etching.3. Failure mechanism of the thin oxide layer between two polysilicon is the oxide layer between two polysilicon over etching, resulting filling up the gate polysilicon too much, and etching is not sufficient, residues is formed and shortened source polysilicon contact. The improvement program is to optimize the oxide layer between two polysilicon and gate polysilicon etching conditions.Through summarizing failure analysis of Trench MOSFET of the article, there is more complete understanding of failure analysis, affording some guide to failure analysis, yield enhancement and product quality improvement of Trench MOSFET and other semiconductor devices in the future.