Research And Design Of 60 GHz Injection-Locked Frequency Divider In 40nm CMOS

The current variety of wireless communication technologies can not meet the application requirements because of the limited spectrum and communication rate. Millimeter-wave wireless communication technology is the current research focus with 5-7GHz unlicensed spectrum resources and multi-Gbps communication rate. Meanwhile, the high-frequency performance of CMOS device is improved continuously with the rapid development of CMOS technology. CMOS proscess has the advantages of low-cost, high integration and is compatible with the base-band modules, which make it optimal choice for millimeter-wave CMOS integrated circuits.Voltage-controlled oscillators (VCO) and dividers work at the highest frequency as core components in the phase-locked loop (PLL) frequency synthesizer, whose performances will directly affect the performance of the entire transceiver system. Based on SMIC 40nm CMOS proscess, a VCO and an injection-locked frequency divider (ILFD) were designed applied for the millimeter-wave PLL. The main work and achievements are as follows:1. Passive devices inductors and transmission lines were designed and optimized for millimeter-wave band using electromagnetic simulators ADS and HFSS to meet the design requirements. Equivalent circuits of inductors were modeled to optimize circuit design and improve simulation accuracy. Accumulation-mode MOS varactors were adopted after analyzing and comparing the pros and cons of several common varactors.2. An injection-locked frequency divider (ILFD) was designed based on SMIC 40nm CMOS process. Injection efficiency was enhanced by optimizing the injection network and device size. A differential inductor was designed and optimized using electromagnetic simulator to extend the locking range. Layout was designed and optimized to reduce the parasitic effects, mismatches and interferences. Post-simulation shows that the ILFD has a locking range of 6.0GHz from 55.2GHz to 61.2GHz and consumes 5.5mW (excluding buffers) from a 0.8V power supply. The core chip area is 0.016mm2. The ILFD meets the demands for low power consumption, small area and wide locking range.3. A voltage-controlled oscillator (VCO) with low power consumption and wide tuning range was designed based on SMIC 40nm CMOS process. The oscillation frequency was enhanced and the minimum required loop gain was decreased by using the distributed LC tank. Phase noise was optimized and the frequency tuning range was enhanced by optimizing the design of varactors in the LC tank. The quality factor and phase noise was improved due to the proposed inductor which was designed and modeled by using electromagnetic simulator. Post-simulation shows that the VCO has a tuning range of 5.1 GHz (8.7%) from 56.1 GHz to 61.2GHz. The phase noise is-88dBc/Hz at 1 MHz offset at the center frequency. The VCO consumes 3.3mW (excluding buffers) from a 0.8V power supply and the chip area is 0.0135mm2. The output signal of the VCO acts as the input signal of the ILFD and the output frequency is divided. United-simulation of the VCO and ILFD verifies the theory of phase noise and indicates that the VCO and divider are applicable for millimeter-wave phase-locked loop frequency synthesizer.