Research & Implementation Of Paper Defect Detection Preprocessing System Based On FPGA

The paper defect which is caused in the process of papermaking will affect the quality of the paper seriously due to the worn equipment, raw material or environmental pollution. Traditional paper defect detection system is costly because it uses high speed computer to recognize and classify paper defect. The high speed computer completes complex image processing algorithms, such as filtering, edge detection and pattern recognition algorithm. Under the support of Shaanxi Province innovation project co-ordinator(item number: 2012KTCQ01-19), this paper in-depth analyses paper defect detection’s principle and expands application technology research around paper image acquisition, preprocessing algorithm and data transmission. The paper defect detection preprocessing system based on FPGA is designed for the characteristics of real-time requirements and large data which the paper defect detection meets. The system preprocesses paper image after acquiring the data, and then transmits to the computer for further recognition and classification. The system reduces production cost by using common computer instead of high-speed computer without affecting real-time. The main work can be summarized as follows:1) The design of paper defect detection preprocessing system based on FPGA. The solution of paper defect detection preprocessing system based on FPGA is identified after analyzing the principle of paper defect detection based on machine vision. The system caches data to memory after capturing the image via Camera Link interface, and then processes the image by preprocessing algorithm. The image data is transmitted to computer via PCIe interface, finally. The core of system is frame grabber & processor, which increases processing function on a common frame grabber.2) The design of paper defect detection experimental platform. The paper defect detection experiment platform is designed in order to simulate the field paper defect detection process. The platform includes paper roll holder, light and camera, which the design of light and the selection of camera are the key focus of the platform.3) The design of image grabber & processor’s hardware circuit. The existing frame grabber can not be secondary development due to the intellectual property protection. Therefore, the image grabber & processor hardware circuitry is designed after in-depth study of the internal structure of CCD line scan camera. The main circuit of image grabber & processor includes FPGA, Camera Link circuit, PCIe Goldfinger circuit and memory circuit. Receiver DS90CR2888 A, driver DS90LV047 and receiver/driver DS90LV019 are the signal converter chip between Camera Link and FPGA. The grabber & processor is connected with camera via MDR26 connector, and it can be plugged into the computer’s PCIe slot.4) HDL implementation of each module within the FPGA. FPGA has the flexibility of software and the parallelism of hardware, it can control the camera, memory and other external devices via configuring the interface. Meanwhile, it can parallel preprocess the paper image data. In Top-Down design pattern for FPGA design process, the entire system is divided into image acquisition module, memory interface module, PCIe bus interface module and paper image preprocessing module. Image acquisition module control the camera to capture the paper image via Camera Link interface. Memory interface module design two ram to match the transfer rate for DDR2 SDRAM. In PCIe bus interface module, two data transfer mode, memory access and high-speed DMA, are designed. Middle filter model and edge detection model are completed in DSP Builder environment, and the models are transformed into HDL.5) The simulation of each module within FPGA and the test of experimental system. In order to verify the correctness of each module within FPGA, the functional simulation is designed in Modelsim software. The paper defect detection preprocessing system is tested in the paper defect detection experimental platform. When the motor speed is 80 r/min, the speed of paper is about 25 cm/s, the camera’s line frequency should be about 2000 Hz. When the line frequency of camera is adjusted to 2000 Hz, the system obtains the paper image which is almost as same as the real image. When the line frequency is adjusted to others, the image is not as same as real image. The test indicates the system has reached the target.This design of paper defect detection preprocessing system based on FPGA completes median filtering and edge detection before transmitting the data to computer. It can reduce the amount of computation and the complexity of algorithm for computer. So the common computer can instead of high-speed computer, it is expected to reduce the cost of paper defect detection. Meanwhile, the system is portable, and can be applied to other industries detection.