Development Of Paper Defect Pretreatment System Based On FPGA

With the continuous development of paper industry, paper machine speed isfaster and paper banner is wider. During the production, paper defects such asfolds, gaps, holes and stains, are caused by equipment abrasion, raw material andenvironment pollution or other reasons. Paper defects affect paper quality. It isnot easy to inspect them by manual inspection. In practical production, it isimportant to monitor production quality by judging the disease type of a paperand finding out causes.Machine vision detection technology has advantages of non-contact, fastspeed, high precision, intelligent, etc. It has become the focus of future webinspection systems. Nowadays, most web inspection systems which usecomputer to achieve image acquisition, processing and next control, have manyproblems, such as, lack of real-time, too large data, and heavy load of computerand so on. A paper defects detection hardware structure based on FPGA ispresented. The main work is summarized as follows.1) The paper defects detection pretreatment scheme is identified based onFPGA. This paper introduces the concept and origin of paper diseases, afteranalyzing the current research status of paper disease detection. The pretreatmentscheme based on FPGA is determined in this paper disease detection system,each function module of the system is detailedly classified.2) Image acquisition is completed by FPGA.The control of image sensorwith FPGA, mainly includes the camera register configure(image resolution,gain, frame rate, etc.) with I2C bus, the line and field signal acquisition anddigital image data captured, Bayer pattern array to RGB888conversion, RGB888to YUV422conversion. Only grayscale images were discussed in thisWeb inspection algorithm, the subsequent algorithm including contrastenhancement, mean filtering, Gaussian filtering, median filtering and edgedetection all just aim at the luminance component (Y component of YUV422).3) The acceleration of paper defects image processing algorithms is realizedwith FPGA hardware. This thesis expatiates the principle and strategy for FPGAdesign and elementarily studies parallel structure of algorithm for FPGA imageprocessing. Through improving algorithms and optimizing structures, inconditions of efficiently using hardware resource, the utility of the parallelalgorithm is exploited more efficiently in the design. With pipeline optimizationalgorithm, module speed of dealing with images is largely improved. FPGA canbe used to achieve the hardware acceleration of image processing algorithm.Firstly, paper images taken by high-speed camera are preprocessed with FPGA.Secondly, the position and size of paper defects areas are preliminary determined.And then, these above information can be sent to a computer for furtheridentification and classification.4)Completed the design of the system and on-line verification.Inaccordance with the requirements of system functions, choosing the appropriatechips for designing circuit diagram, making PCB plate, designing the drive of allmodules are done. The system mainly consists of five parts, FPGA(EP2C5T114C8) core control module, FPGA configuration (EPCS4) module,CMOS image sensor (MT9V031) module, SDRAM (HY57V641620FTP) imagebuffer module, VGA (ADV7123) display module.Tests show that web inspection pretreatment device designed in this papercan display and pretreated paper defects in real-time. At the same time, FPGA isas the core of this system, the flexibility, the easiness to modify, the testcharacteristic, and the automatic upgradability of the system can be enhanced.Meanwhile, it also has advantages of low design cost, short developing cycletime and real-time performance.