Research And Implementation Of A Configurable High-performance FFT Processsor

With the development of technology of electronics and integrated circuit, digital signal processing is now widely used in many fields such as communication, signal processing, biomedicine and automatic control. As a basic transformation in digital signal processing, Discrete Fourier Transformation (DFT) and its fast algorithm, FFT, is becoming more and more important. Especially in recent years, the research on high-speed FFT processor is driven further by the development of 4G communication technology using ODFM.FFT was born in the 1960s and has become mature during the last 40 years. However, how to implement FFT with circuit is still a hot topic because the algorithm is complicated but in order. For example, we can use parallelism to adapt FFT to different resource and data size. In addition, pipeline can be used to reach a higher operating frequency.In this paper, the author has compared several FFT algorithms and finally selected Radix-8 as the main part. Meanwhile Radix-2, Radix-4 and 2D-FFT algorithm are also supported. Such a combination makes the design able to process different input data size. Compared to completely Radix-2, this combination of algorithms consumes one third of the time in calculation and gets higher accuracy with similar resource consumption.The author designed a lightweight butterfly structure which is as small as one eighth of a whole Radix-8 butterfly unit. In this structure, pipeline is introduced to make the circuit work at 1GHz and get a throughput of 1 data-point per cycle. Except the control unit, all modules are tube-like and scaleable. With different numbers of tubes in parallism, the design can meet varios demands of resource and performance in different environment.For better reusability, the author design a module named DMA_PORT to transport data. With this module, the FFT processor can support direct/inverse input or output, IFFT calculation and data transportation in 2D-FFT algorithm.For higher accuracy, an optimization of twiddle factor is introduced in addition to the Radix-8 algorithm. In the FFT processor, the related module uses the constants which are stored in two 8KB SRAM to calculate the twiddle factors in real time. After optimization of the calculation and analyzation of the symmetry, one multiplication is needed to get one twiddle factor. With such optimization, the SNR of this FFT processor can be higher than 130dB.After function verification, FPGA verification and after-layout verification, the FFT processor is able to get accurate results. Synthesis and sample show that the design can work at 1GHz which means that the processor meets the demand of high-speed signal processing.