Research Of High Performance Multi-parameter Dynamically Configurable Viterbi Decoder

Convolutional code is one of error correction coding methods,which has good error correction performance.Since the Viterbi algorithm,one of the best decoding algorithms of convolutional code,is put forward,the convolutional encoder coupled with the Viterbi decoder has been widely used in various kinds of digital error correction systems.As the developing of multi-mode technology,more and more systems require digital signal processing cells to be compatible with a variety of network patterns,and each kind of pattern corresponds to different parameters of convolutional code,so the multi-parameter configurable Viterbi decoder needs to be developed.This thesis proposes a design thought of multi-parameter configuration realization based on the basic parameters of the convolutional code and the influences of various parameters on Viterbi decoder structure.The research and design of a high performance configurable Viterbi decoder is finally completed from the principle design,circuit design,area optimization,to simulation and synthesis processes.The main content of this thesis is summarized as follows.1)The basic structure of the Viterbi decoder is analyzed by analyzing the influences of code rate,constraint length and constraint polynomial on internal modules of Viterbi decoder.Then it is determined to realize the multi-parameter configurable Viterbi decoder by the way of structure topology and optimization.2)The new structure of configurable Viterbi decoder is presented,and two new functional units,configuration unit(CU)and standard convolutional symbol generator(SCSG)are designed.CU makes dynamic adjustments to input symbols and polynomials of Viterbi decoder according to the code rate and constraint length,and generates the modified symbols and modified polynomials.SCSG calculates the standard convolutional symbol corresponding to current state based on the standardized polynomial in real-time.Besides,the BranchMetric unit and StateMetric unit are improved.Branch Metric unit dynamically calculates branch metrics according to the modified symbols and standard convolutional symbol.StateMetric unit structures trellis diagram according to the code rate and constraint length,and generates transition paths,with the method of full parallel to calculate state metrics.The calculations of SCSG,BranchMetric unit and StateMetric unit are all associated with the current state,three units are formed a self-aligned network,which can dynamically adjust mapping relationship according to the variation of the input parameter,in order to achieve the dynamic configuration of Viterbi decoder.The configurable Viterbi decoder designed in this work can support variable code rates of 1/2,1/3,1/4 and variable constraint length 3-9,as well as arbitrary constraint polynomial per bit,with throughput up to 200 Mbps.3)The Odd-Even Discretely Reused and Equivalent Euclid Distance methods are proposed on the basis of the configurable Viterbi decoder structure,with the goal of achieving optimal area optimization design and in view of SCSG and BranchMetric Unit.In the SCSG,it adopts iterative operation way to preferentially calculate standard convolutional symbols of all even states,and then reuse the standard convolutional symbols of even states to calculate standard convolutional symbol of all odd states,thus the repeated calculation of low bits is reduced.In BranchMetric unit,it adopts “1-norm” instead of “2-norm” of vector difference to carry on equivalent approximate calculation of Euclidean distance,thus reduce the complexity of calculating branch metric values.After the SCSG and BranchMetric unit are optimized by using Odd-Even Discretely Reused and the method of Equivalent Euclid Distance,the numbers of logic gates are 12 k and 20 k,reduced by 33.3% and 54.5%,respectively.4)After RTL design of the configurable Viterbi decoder completes,the simulations of each module and the whole decoder are conducted to demonstrate the validity of the configurable Viterbi decoder.MATLAB is adopted to establish the model of communication system based on the Viterbi decoding algorithm,and the error-correcting performance of configurable Viterbi decoder is evaluated through adding Gaussian white noise in channel.For all the parameters,when the signal-to-noise ratio(SNR)of system is 6 dB,the error rate of system is less than 0.1%,the lowest rate can be 0.0001 ‰,and such an error-correcting performance will make the Viterbi decoder suitable to most communication standards.It can be concluded that the configurable Viterbi decoder designed in this thesis has high flexibility.Besides the commonly-used code rates such as 1/2 and 1/3,it also has good compatibility for the code rate of 1/4 communications standard.In addition,through the optimization design,the decoder has higher throughput and limits the number of logic gates to 159.5 k at the same time.Compared with related research work,its logical resource consumption is reduced by about 16% and the throughput is increased by about 230%.