Researches And FPGA Implementation Of Cell Search For TD-LTE

LTE is the mainstream technology of mobile communication system evaluating from3G to4G, which can support variety-bandwidth network and provide a peak downlink rate above100Mbps. Also it reduces the system delay significantly by adopting IP-based network, and improves user’s data rate on the edge of a cell. TD-LTE is an important technology in LTE, which uses different timing to distinguish data in downlink from that in uplink. Cell search is the first step for communication equipments to access the TD-LTE system. So it is important that the subsequent communication process could be carried out smoothly. FPGA which changes mathematical algorithm to hardware circuit on the chip by programming and runs in parallel is one kind of chips that support programming. Data can be processed fast and in real-time on the FPGA chip. Now, the system in which the communication rate is increasing nowadays needs chip to run mathematical algorithms faster than ever before, so the FPGA chip is used widely in electronic communication systems. According to the explanation above, the research on how to design the algorithm of cell search of TD-LTE system on FPGA chip has a practical significance.This paper researches the existing arithmetic of cell search, and summarizes one kind of practical arithmetic of cell search, which considers structure of the arithmetic and processing speed of the FPGA chip, and has lower complexity under the premise of good performance. In the procedure of the coarse synchronization of PSS, we propose a matched filtering algorithm with down sampling frequency choosing as the eight times of the signal’s frequency. In this algorithm, firstly, we process the signal using the eight times down sampling method. Then, calculate the correlation between the processed signals with three kinds of local down sampled PSSs. The local PSS that carries out the maximum correlated peaks is selected as the PSS. Based on this algorithm, the approximate range of the PSS can be located rapidly, which can improve the efficiency of the system. When it comes to the fine synchronization, an algorithm with the window’s length of seventy-three sampling points is presented. These seventy-three sampling points, which will be set as the head of the test synchronous signal, are located beside the coarse synchronous signal. Then, the correlation results between these test signals and the local synchronous signal is extracted. And, the test signal with maximum correlated peaks is determined as the final synchronous signal. This algorithm is characterized by its relatively low complexity. The synchronization algorithm using equal-length frequency offset signal array is adopted.The correlation results between the signal array and the PSS are carried out. The signal with maximum correlated peaks is chosen as the result of the coarse frequency offset estimation. In the process of the coarse frequency offset estimation, a frequency-phase mapping method is adopted. In this method, the result can be extracted by multiplying the phase difference between the PSS and the SSS by a coefficient. Compared with the conventional CORDIC algorithm, this algorithm is featured by its higher speed. Then, a simulation platform for the arithmetic using MATLAB is taken to verify the performance of these sub-modules. The performance of sub-modules meets the design requirements.Based on the above simulation platform, I migrate the arithmetic of cell search to a Xilinx K7FPGA chip, than test its function and performance. Resource usage of K7Xilinx and stability of system should be considered when design the Verilog program to make the system run at an optimum status.