This topic designs a radar Detector,it is for regular maintenance of radar in the use of the testing equipment,used to repair one responsible for control of the power of the radar extension and signal the operation of the extension,and find the two sets of extension fault.This subject using EDA technology,with CPLD as the core in the course of the study, uses the standard frequency provided by the radar and the oscillating circuit,realizes the measurement and displays the pulse frequency,the time of two way pulse interval tec.fuction. this design uses aEPM240T100chip of series MAX II from ALTEAR company. Uses EPM240T100to realize all logic function within the detector. Use prescaler or trigger output pulse width of the gate control CPLD count, and will be counting the results through the panel LED pipe display,in the end according to shine the light of pipe into the corresponding frequency conversion or time. It can use VHDL Language programming to finish CPLD software design,programming,debugging, simulation and download on the platform Quartus Ⅱ afford by ALTEAR company.This paper has particularly described the top-to-bottom design method of thesystem, the circuit composite of the hardware and the software program device of CPLD,and to make the whole system software and hardware debugging.Finally,using the specific verification instrument,according to the actual testing procedures measurement,through the test to validate the system all the indexes comply with the design requirements.The system fully used CPLD’s high levels of integration,flexible programming, design and manufacture of the characteristics of low cost,not only greatly shorten the development cycle development,but also make the system with compact structure,small volume,high reliability,and improve the maintainability,etc. |