Research And Development Of LVS Verification System In The PDK Suite

Process Design Kit（PDK）is a complete set of files provided, for analog/mix-ed-signal IC circuit design. It is a bridge in between fabless IC design companies,foundries and EDA companies. In today’s semiconductor industry, the manufactur-ingprocess plays an indispensable role. The quality of PDK will directly affect theefficiency and quality of the whole process of development.In this thesis, the major task is aimed at PDK suite of the LVS (Layout ver-sus Schematic) commandfile developed for a more complete verification system.0.5um process has been used as the manufacturing technology. Synopsys Laker is usedas a software platform. Script languages such as Perl and tcl have been used forautomation. Through the study of traditional PDK validation method, the authorfound it time-consuming and with a narrow coverage. In this thesis, the author pro-poses a more complete and effective new verification specification. The methodcovers different procedures including interface development, selection of input para-meters, test pattern generation and analysis of test report to elaborate the workingprinciple of a verification system. The practice shows that this method not only im-proves the modeling speed, but also greatly improves the productivity of modeling,meanwhile producing PDK with high coverage testing models.Through a large number of technological process of the test, the LVS verifi-cation system has reached the originally goals set. With the development of semi-conductor manufacturing process, the parameters and functions contained in PDKwill also become increasingly complex. Hence, PDK verification system in the PDKwill play an increasingly important role in the development procedure.