Design And Implementation Of Harmonics Analyzer In Power Systerm Based On FPGA

The pollution of the power harmonics in power grids is more and more serious and causes tremendous harm to the power grids and the electrical equipments. It is the premise to correctly measure the harmonics in the power grid for restraining the harm of the harmonic. Therefore, the real-time detection and analysis to the harmonics in power grids is significant in theory and engineering.At present, the most of the harmonic analysis systems adopts the design of hardware architecture with dual-processor. The design could meet the requirement of the system control and the complex computing for the detection algorithm. However, the circuit structure of the design is complex. The communication between processors relies on the data bus outside the processor, and the data exchange speed is limited. The data processing in the processor runs in the way of serial execution. And, the processing speed is limited by the pipeline. In order to improve system speed, the paper comes up with a solution of harmonic signal acquisition and processing system based on FPGA and SOPC technology. In front of the system, the acquisition and processing of the harmonic is implemented by hardware, which takes full advantage of hardware acceleration. And the system uses the soft-core processor Nios II for further operations and control, which could be completed through on-chip bus in FPGA. That solves the bottleneck of the data transmission and makes full use of high speed of hardware design and flexibility of control by processor Nios Ⅱ.The chip AD7606, the operational amplifier OPA2227, the current and voltage sensors, are adopted to accomplish the circuit design of harmonic signal acquisition and conditioning. Then, the Verilog HDL hardware description language is used to design and accomplish the harmonic signal acquisition and processing, including the hardware modules for the driving and data collection of ADC, adding Blackman window to the collecting data, and floating-point FFT computation with local pipeline architecture. Moreover, the timing simulation of above hardware modules through Modelsim is verified. In order to complete the further relevant computation and control, the soft-core processor Nios Ⅱ is introduced to achieve the software programming, overall scheduling, reading the result of FFT computation, bimodal interpolation, and calculating harmonic parameters. For better human-computer interaction, LTM IP core is designed and accomplished, which is added to the bus of processor for automatically reading the corresponding display information. At last, the paper uses the DE2-70development board to verify the design and achieve the harmonic detection system.Finally, related testing and analysis for the system is done. Under the system clock of100MHz, the front processing module can finish a1024-point floating-point FFT calculation within77us and the soft-core processor Nios II can complete one way calculation of harmonic signal interpolation and harmonic parameters within78ms. In practice, the system can meet the needs of real-time detection. The result of related testing and analysis shows that the system is stable and has high detection accuracy, high processing speed.