Hardware Acceleration Design Technology For High Density Computing Many-core

NoC is the communication architecture of the many-core SoC,and it has features of high parallelism,strong scalability,and rich low-power mechanism.It is widely applied in high-density computing area.Artificial intelligence algorithms have high-density computing properties.Therefore,in the artificial intelligence field,many-core-based hardware acceleration technology has become a hot research topic.How to fully exploit the new features of the on-chip network and artificial intelligence and solve the integrated design issues such as delay and scalability becomes a new challenge.This thesis considers this as the research object and works on following two aspects:(1)Reducing the upper bound of delay using online calculation for configuration parameters,and;(2)Improving computation speed of convolution neural network based on multicast NoC.The main work has the following aspects.(1)Designing online computing configuration conflict optimization hardware.Aiming at the problem of low automation in the quasi-dynamic conflict matrix,this thesis builds a conflict-optimized hardware platform which can calculate and configure online.The hardware platform predicts all network conflict situations according to the current mapping scheme and calculates a dynamic library file.When the NoC works,the hardware platform monitors the real-time conflicts of NoC and adjusts the transmission path and traffic distribution of the target data stream to reduce the degree of congestion on NoC combining the dynamic library file.The experimental results show that there are different degrees of improvement for different mapping schemes.For the network average delay,the proposed method can averagely reduce by 14.57% and for the upper bound of delay,it can averagely reduce by 31.13%.(2)Designing CNN Hardware Acceleration Based on Multicast NoC.To solve the problem of poor scalability in existing CNN acceleration methods,this thesis design and implement CNN hardware accelerators based on a multicast NoC.This design fully explores the feature of data reusing in CNN.It designs and implements a hand-written recognition many-core SoC based on LeNet-5 neural network,which accelerates the process of recognizing hand written digital image.This thesis mounts hardware acceleration units on the nodes of multicast NoC and coordinates the operation of multiple hardware acceleration units to increase the calculation speed.Compared with the existing hardware-based acceleration,the image recognition speed of this thesis is increased by 17.97%.Compared with the CPU-based software acceleration method,the speedup ratio is 5.06.